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1. 发明授权

US07934045B2 Redundant and fault tolerant control of an I/O enclosure by multiple hosts 失效
标题翻译：多个主机对I / O机箱的冗余和容错控制
公开(公告)号：US07934045B2
公开(公告)日：2011-04-26
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

2. 发明申请

US20100312942A1 Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts 失效
标题翻译：冗余和容错控制多个主机的I / O机箱
公开(公告)号：US20100312942A1
公开(公告)日：2010-12-09
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

3. 发明申请

US20080018313A1 POWER SUPPLY SYSTEM USING DELAY LINES IN REGULATOR TOPOLOGY TO REDUCE INPUT RIPPLE VOLTAGE 审中-公开
标题翻译：使用延迟线在调节器拓扑中降低输入纹波电压的电源系统
公开(公告)号：US20080018313A1
公开(公告)日：2008-01-24
申请号：US11458750
申请日：2006-07-20
申请人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G05F1/00
CPC分类号： H02M1/15 , H02M2001/008
摘要： A power supply system for reducing input ripple voltage, the system including: a first switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; a second switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; wherein outputs of the first switching regulator and the second switching regulator are connected to a power bus; a first delay element connected to the synchronization input pin of the first switching regulator; a second delay element connected to the synchronization input pin of the second switching regulator; wherein the first delay element and the second delay element have different delays, the first switching regulator and second switching regulator operating out of phase; and a master clock for providing timing control to the first and second delay elements.
摘要翻译：一种用于减小输入纹波电压的电源系统，该系统包括：具有至少两个输入引脚的第一开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 具有至少两个输入引脚的第二开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 其中所述第一开关调节器和所述第二开关调节器的输出端连接到电源总线; 连接到第一开关调节器的同步输入引脚的第一延迟元件; 连接到第二开关调节器的同步输入引脚的第二延迟元件; 其中所述第一延迟元件和所述第二延迟元件具有不同的延迟，所述第一开关调节器和第二开关调节器异相工作; 以及用于向第一和第二延迟元件提供定时控制的主时钟。

4. 发明授权

US08645652B2 Concurrently moving storage devices from one adapter pair to another 失效
标题翻译：同时将存储设备从一个适配器对移动到另一个
公开(公告)号：US08645652B2
公开(公告)日：2014-02-04
申请号：US12971763
申请日：2010-12-17
申请人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00 , G06F15/16 , G06F15/173
CPC分类号： G06F3/0647 , G06F3/0607 , G06F3/0635 , G06F3/0689
摘要： A mechanism is provided for moving control of storage devices from one adapter pair to another. In a trunked disk array configuration, moving the storage devices from one disk array to another disk array begins by attaching the downstream ports of the two independent disk arrays together. The mechanism redefines one set of the ports as upstream ports and through switch zoning makes a set of devices available to the second disk array adapters. By controlling zoning access and performing discovery one device port at a time, the mechanism transfers access and ownership of the RAID group from one adapter pair to another.
摘要翻译：提供了一种机制，用于将存储设备的控制从一个适配器对移动到另一个。在集群磁盘阵列配置中，将存储设备从一个磁盘阵列移动到另一个磁盘阵列，首先将两个独立磁盘阵列的下游端口连接在一起。该机制将一组端口重新定义为上游端口，并通过交换机分区使一组设备可用于第二个磁盘阵列适配器。通过控制分区访问并一次执行发现一个设备端口，该机制将RAID组的访问权限和所有权从一个适配器对传输到另一个。

5. 发明申请

US20120159069A1 Concurrently Moving Storage Devices from One Adapter Pair to Another 失效
标题翻译：将存储设备从一个适配器对同时移动到另一个
公开(公告)号：US20120159069A1
公开(公告)日：2012-06-21
申请号：US12971763
申请日：2010-12-17
申请人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F12/08
CPC分类号： G06F3/0647 , G06F3/0607 , G06F3/0635 , G06F3/0689
摘要： A mechanism is provided for moving control of storage devices from one adapter pair to another. In a trunked disk array configuration, moving the storage devices from one disk array to another disk array begins by attaching the downstream ports of the two independent disk arrays together. The mechanism redefines one set of the ports as upstream ports and through switch zoning makes a set of devices available to the second disk array adapters. By controlling zoning access and performing discovery one device port at a time, the mechanism transfers access and ownership of the RAID group from one adapter pair to another.
摘要翻译：提供了一种机制，用于将存储设备的控制从一个适配器对移动到另一个。在集群磁盘阵列配置中，将存储设备从一个磁盘阵列移动到另一个磁盘阵列，首先将两个独立磁盘阵列的下游端口连接在一起。该机制将一组端口重新定义为上游端口，并通过交换机分区使一组设备可用于第二个磁盘阵列适配器。通过控制分区访问并一次执行发现一个设备端口，该机制将RAID组的访问权限和所有权从一个适配器对传输到另一个。

6. 发明申请

US20080246453A1 POWER SUPPLY SYSTEM USING DELAY LINES IN REGULATOR TOPOLOGY TO REDUCE INPUT RIPPLE VOLTAGE 审中-公开
标题翻译：使用延迟线在调节器拓扑中降低输入纹波电压的电源系统
公开(公告)号：US20080246453A1
公开(公告)日：2008-10-09
申请号：US11865904
申请日：2007-10-02
申请人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： H02M3/137
CPC分类号： H02M1/14 , H02J1/08 , H02M2001/008
摘要： A power supply system for reducing input ripple voltage, the system including: a first regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a second regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a Nth regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; wherein outputs of the first regulator, second regulator, and Nth regulator are connected to a single power bus or correspondingly to separate power buses; a first delay connected to the synchronization pin of the second regulator; a second delay connected to the synchronization pin of the Nth regulator; wherein the first delay and the second delay have different delays configured for enabling the first regulator, second regulator, and the Nth regulator to operate out of phase; and a master clock for providing timing control to the first and second delay.
摘要翻译：一种用于降低输入纹波电压的电源系统，该系统包括：具有至少两个输入的第一调节器，一个输入端为电压输入引脚，另一个输入为同步引脚; 具有至少两个输入的第二调节器，一个输入为电压输入引脚，另一个输入为同步引脚; 具有至少两个输入的第N调节器，一个输入为电压输入引脚，另一个输入为同步引脚; 其中第一调节器，第二调节器和第N调节器的输出连接到单个电源总线或相应地连接到单独的电源总线; 连接到所述第二调节器的同步引脚的第一延迟; 连接到第N调节器的同步引脚的第二延迟; 其中所述第一延迟和所述第二延迟具有不同的延迟，所述延迟被配置用于使所述第一调节器，所述第二调节器和所述第N调节器不同相工作; 以及用于向第一和第二延迟提供定时控制的主时钟。

7. 发明申请

US20130326270A1 Maximizing Use of Storage in a Data Replication Environment 有权
公开(公告)号：US20130326270A1
公开(公告)日：2013-12-05
申请号：US13484789
申请日：2012-05-31
申请人： Chiahong Chen , John C. Elliott , William G. Sherman
发明人： Chiahong Chen , John C. Elliott , William G. Sherman
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1464 , G06F11/203 , G06F11/2035 , G06F11/2048 , G06F11/2069 , G06F11/2089 , G06F11/2092 , G06F2201/84 , G06F2201/85 , H04L67/1095
摘要： Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device.

8. 发明授权

US08489914B2 Method apparatus and system for a redundant and fault tolerant solid state disk 有权
标题翻译：用于冗余和容错固态盘的方法装置和系统
公开(公告)号：US08489914B2
公开(公告)日：2013-07-16
申请号：US13460496
申请日：2012-04-30
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Andrew D. Walls
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Andrew D. Walls
IPC分类号： G06F11/07
CPC分类号： G06F11/2094 , G06F11/2089 , G06F11/2092 , G06F11/2097
摘要： A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive.
摘要翻译：固态驱动器包括第一固态盘控制器（SSDC），第二SSDC和闪存阵列。闪存阵列包括第一闪存端口和第二闪存端口。第一个SSDC配置为通过第一个闪存端口连接到闪存阵列，第二个闪存阵列被配置为通过第二个闪存端口连接到闪存阵列。第一个SSDC和第二个SSDC都配置为连接到闪存阵列中的所有内存，而第一个SSDC，第二个SSDC和闪存阵列位于公共固态驱动器内。

9. 发明授权

US07917713B2 Optimized data migration with a support processor 失效
标题翻译：使用支持处理器优化数据迁移
公开(公告)号：US07917713B2
公开(公告)日：2011-03-29
申请号：US11613858
申请日：2006-12-20
申请人： John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G06F12/00
CPC分类号： G06F11/2094 , G06F11/1658 , G06F11/1662 , G06F11/2082
摘要： A system migrates data between a source device and a target device in a storage system. A processor is operational within a local domain of the storage system. A redundant array of independent disks (RAID) controller electrically connected to the processor. The RAID controller divides a capacity of the source device into a plurality of sub-regions, locks the sub-regions from storage activity, establishes a mirroring relationship for write data updates between the source device and target device, and assigns the processor to copy data from the source device to the target device. A method of migrating data includes dividing a capacity of a source device into a plurality of sub-regions, locking the sub-regions from storage activity, establishing a mirroring relationship for write data updates between the source device and a target device, and assigning a local processor to copy data from the source device to the target device.
摘要翻译：系统在存储系统中的源设备和目标设备之间迁移数据。处理器在存储系统的本地域内可操作。电连接到处理器的独立磁盘冗余阵列（RAID）控制器。 RAID控制器将源设备的容量划分为多个子区域，将子区域从存储活动中锁定，为源设备和目标设备之间的写入数据更新建立镜像关系，并分配处理器复制数据从源设备到目标设备。迁移数据的方法包括将源设备的容量划分为多个子区域，将子区域与存储活动锁定，建立用于源设备和目标设备之间的写入数据更新的镜像关系，以及分配本地处理器将数据从源设备复制到目标设备。

10. 发明申请

US20090327578A1 Flash Sector Seeding to Reduce Program Times 有权
标题翻译：闪光灯播种减少节目时间
公开(公告)号：US20090327578A1
公开(公告)日：2009-12-31
申请号：US12146098
申请日：2008-06-25
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.
摘要翻译：非易失性闪速存储器包括多个非易失性存储器，其中第一非易失性存储器与所有非易失性存储器被预编程（擦除），并且至少第二非易失性存储器被预编程有种子值，利用减少的编程时间少于六个零。当写入（编程）数据字节时，存储器系统在一个或多个种子表中查找数据字节，以确定存储器系统可以用减少的编程时间写入数据字节的非易失性存储器的一部分。然后，存储器系统将数据字节的位置记录在地址转换表中，以便可以访问数据字节。

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