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1. 发明申请

US20120159069A1 Concurrently Moving Storage Devices from One Adapter Pair to Another 失效
标题翻译：将存储设备从一个适配器对同时移动到另一个
公开(公告)号：US20120159069A1
公开(公告)日：2012-06-21
申请号：US12971763
申请日：2010-12-17
申请人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F12/08
CPC分类号： G06F3/0647 , G06F3/0607 , G06F3/0635 , G06F3/0689
摘要： A mechanism is provided for moving control of storage devices from one adapter pair to another. In a trunked disk array configuration, moving the storage devices from one disk array to another disk array begins by attaching the downstream ports of the two independent disk arrays together. The mechanism redefines one set of the ports as upstream ports and through switch zoning makes a set of devices available to the second disk array adapters. By controlling zoning access and performing discovery one device port at a time, the mechanism transfers access and ownership of the RAID group from one adapter pair to another.
摘要翻译：提供了一种机制，用于将存储设备的控制从一个适配器对移动到另一个。在集群磁盘阵列配置中，将存储设备从一个磁盘阵列移动到另一个磁盘阵列，首先将两个独立磁盘阵列的下游端口连接在一起。该机制将一组端口重新定义为上游端口，并通过交换机分区使一组设备可用于第二个磁盘阵列适配器。通过控制分区访问并一次执行发现一个设备端口，该机制将RAID组的访问权限和所有权从一个适配器对传输到另一个。

2. 发明申请

US20080246453A1 POWER SUPPLY SYSTEM USING DELAY LINES IN REGULATOR TOPOLOGY TO REDUCE INPUT RIPPLE VOLTAGE 审中-公开
标题翻译：使用延迟线在调节器拓扑中降低输入纹波电压的电源系统
公开(公告)号：US20080246453A1
公开(公告)日：2008-10-09
申请号：US11865904
申请日：2007-10-02
申请人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： H02M3/137
CPC分类号： H02M1/14 , H02J1/08 , H02M2001/008
摘要： A power supply system for reducing input ripple voltage, the system including: a first regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a second regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a Nth regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; wherein outputs of the first regulator, second regulator, and Nth regulator are connected to a single power bus or correspondingly to separate power buses; a first delay connected to the synchronization pin of the second regulator; a second delay connected to the synchronization pin of the Nth regulator; wherein the first delay and the second delay have different delays configured for enabling the first regulator, second regulator, and the Nth regulator to operate out of phase; and a master clock for providing timing control to the first and second delay.
摘要翻译：一种用于降低输入纹波电压的电源系统，该系统包括：具有至少两个输入的第一调节器，一个输入端为电压输入引脚，另一个输入为同步引脚; 具有至少两个输入的第二调节器，一个输入为电压输入引脚，另一个输入为同步引脚; 具有至少两个输入的第N调节器，一个输入为电压输入引脚，另一个输入为同步引脚; 其中第一调节器，第二调节器和第N调节器的输出连接到单个电源总线或相应地连接到单独的电源总线; 连接到所述第二调节器的同步引脚的第一延迟; 连接到第N调节器的同步引脚的第二延迟; 其中所述第一延迟和所述第二延迟具有不同的延迟，所述延迟被配置用于使所述第一调节器，所述第二调节器和所述第N调节器不同相工作; 以及用于向第一和第二延迟提供定时控制的主时钟。

3. 发明授权

US08645652B2 Concurrently moving storage devices from one adapter pair to another 失效
标题翻译：同时将存储设备从一个适配器对移动到另一个
公开(公告)号：US08645652B2
公开(公告)日：2014-02-04
申请号：US12971763
申请日：2010-12-17
申请人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Gary W. Batchelor , Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00 , G06F15/16 , G06F15/173
CPC分类号： G06F3/0647 , G06F3/0607 , G06F3/0635 , G06F3/0689
摘要： A mechanism is provided for moving control of storage devices from one adapter pair to another. In a trunked disk array configuration, moving the storage devices from one disk array to another disk array begins by attaching the downstream ports of the two independent disk arrays together. The mechanism redefines one set of the ports as upstream ports and through switch zoning makes a set of devices available to the second disk array adapters. By controlling zoning access and performing discovery one device port at a time, the mechanism transfers access and ownership of the RAID group from one adapter pair to another.
摘要翻译：提供了一种机制，用于将存储设备的控制从一个适配器对移动到另一个。在集群磁盘阵列配置中，将存储设备从一个磁盘阵列移动到另一个磁盘阵列，首先将两个独立磁盘阵列的下游端口连接在一起。该机制将一组端口重新定义为上游端口，并通过交换机分区使一组设备可用于第二个磁盘阵列适配器。通过控制分区访问并一次执行发现一个设备端口，该机制将RAID组的访问权限和所有权从一个适配器对传输到另一个。

4. 发明申请

US20080018313A1 POWER SUPPLY SYSTEM USING DELAY LINES IN REGULATOR TOPOLOGY TO REDUCE INPUT RIPPLE VOLTAGE 审中-公开
标题翻译：使用延迟线在调节器拓扑中降低输入纹波电压的电源系统
公开(公告)号：US20080018313A1
公开(公告)日：2008-01-24
申请号：US11458750
申请日：2006-07-20
申请人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
发明人： Brian J. Cagno , John C. Elliott , Enrique Q. Garcia
IPC分类号： G05F1/00
CPC分类号： H02M1/15 , H02M2001/008
摘要： A power supply system for reducing input ripple voltage, the system including: a first switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; a second switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; wherein outputs of the first switching regulator and the second switching regulator are connected to a power bus; a first delay element connected to the synchronization input pin of the first switching regulator; a second delay element connected to the synchronization input pin of the second switching regulator; wherein the first delay element and the second delay element have different delays, the first switching regulator and second switching regulator operating out of phase; and a master clock for providing timing control to the first and second delay elements.
摘要翻译：一种用于减小输入纹波电压的电源系统，该系统包括：具有至少两个输入引脚的第一开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 具有至少两个输入引脚的第二开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 其中所述第一开关调节器和所述第二开关调节器的输出端连接到电源总线; 连接到第一开关调节器的同步输入引脚的第一延迟元件; 连接到第二开关调节器的同步输入引脚的第二延迟元件; 其中所述第一延迟元件和所述第二延迟元件具有不同的延迟，所述第一开关调节器和第二开关调节器异相工作; 以及用于向第一和第二延迟元件提供定时控制的主时钟。

5. 发明授权

US07934045B2 Redundant and fault tolerant control of an I/O enclosure by multiple hosts 失效
标题翻译：多个主机对I / O机箱的冗余和容错控制
公开(公告)号：US07934045B2
公开(公告)日：2011-04-26
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

6. 发明申请

US20100312942A1 Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts 失效
标题翻译：冗余和容错控制多个主机的I / O机箱
公开(公告)号：US20100312942A1
公开(公告)日：2010-12-09
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

7. 发明申请

US20120239867A1 Flash Sector Seeding to Reduce Program Times 有权
标题翻译：闪光灯播种减少节目时间
公开(公告)号：US20120239867A1
公开(公告)日：2012-09-20
申请号：US13487797
申请日：2012-06-04
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location,of the data byte in an address translation table so the data byte may be accessed.
摘要翻译：非易失性闪速存储器包括多个非易失性存储器，其中第一非易失性存储器与所有非易失性存储器被预编程（擦除），并且至少第二非易失性存储器被预编程有种子值，利用减少的编程时间少于六个零。当写入（编程）数据字节时，存储器系统在一个或多个种子表中查找数据字节，以确定存储器系统可以用减少的编程时间写入数据字节的非易失性存储器的一部分。然后，存储器系统将数据字节的位置记录在地址转换表中，以便可以访问数据字节。

8. 发明授权

US08037380B2 Verifying data integrity of a non-volatile memory system during data caching process 有权
标题翻译：在数据缓存过程中验证非易失性存储器系统的数据完整性
公开(公告)号：US08037380B2
公开(公告)日：2011-10-11
申请号：US12169273
申请日：2008-07-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G11C29/00 , G06F13/00
CPC分类号： G06F11/1064 , G11C29/56 , G11C2029/0407
摘要： To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
摘要翻译：为了确保非易失性闪存的完整性，控制器使用背景测试模式对非易失性存储器进行编程，并在上电自检（POST）操作期间验证非易失性存储器。结合验证非易失性存储器，控制器可以定期地将诊断和状态报告给存储控制器。作为存储控制器上电程序的一部分，存储控制器通过由存储控制器监视的I2C寄存器向控制器发出POST命令。存储控制器可以确定非易失性闪存在没有任何缺陷的情况下起作用，并且控制器可以从非易失性闪存移除电力以扩展其可靠性。定期地，在后台，控制器可以运行诊断例程来检测与易失性存储器和控制器本身相关联的任何故障。

9. 发明授权

US07974189B2 Apparatus and method to set the signaling rate of a network disposed within an information storage and retrieval system 失效
标题翻译：设置信息存储和检索系统中设置的网络的信令速率的装置和方法
公开(公告)号：US07974189B2
公开(公告)日：2011-07-05
申请号：US12196155
申请日：2008-08-21
申请人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
发明人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
IPC分类号： G01R31/08
CPC分类号： H04L41/0896
摘要： A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.
摘要翻译：公开了一种设置网络速度的方法。该方法提供与系统控制器和多个交换机域互连的网络，其中这些多个交换机域中的每一个包括一个或多个信息存储设备和交换机域控制器，并且由多个交换机域中的每一个设置信令该交换机域的速率。所述方法由所述系统控制器对所述交换机域的信令速率的所述多个交换机域中的每一个进行带内查询，并且通过所述多个交换机域中的每一个提供所述交换机域的信令速率的带内。该方法由系统控制器向系统控制器提供指定第一网络速度的第一速度选择命令，并且由多个交换机域中的每一个将该交换机域的信令速率复位到第一网络速度。

10. 发明授权

US07535832B2 Apparatus and method to set the signaling rate of a switch domain disposed within an information storage and retrieval system 失效
标题翻译：设置信息存储和检索系统中设置的交换机域的信令速率的装置和方法
公开(公告)号：US07535832B2
公开(公告)日：2009-05-19
申请号：US10995459
申请日：2004-11-22
申请人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas
发明人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas
IPC分类号： H04L12/26
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0632 , G06F3/0635 , G06F3/0683
摘要： A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating speed comprises a first signaling rate, then the method asserts first Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using that first signaling rate. If the switch domain target operating speed does not comprise the first signaling rate, then the method asserts second Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using a second signaling rate.
摘要翻译：公开了一种设置信息存储和检索系统中设置的交换机域的信令速率的方法。该方法建立交换机域目标操作速度，并确定交换机域目标操作速度是否包括第一信令速率。如果切换域目标操作速度包括第一信令速率，则该方法将第一设备控制代码位置为多个数据存储设备中的每一个，并且多个数据存储设备中的每一个与该交换机使用该第一信令速率。如果切换域目标操作速度不包括第一信令速率，则该方法将第二设备控制代码位置为多个数据存储设备中的每一个，并且多个数据存储设备中的每一个使用第二信令速率与交换机通信信号速率。

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