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1. 发明申请

US20080301345A1 MULTI-CHARACTER ADAPTER CARD 失效
标题翻译：多字符适配卡
公开(公告)号：US20080301345A1
公开(公告)日：2008-12-04
申请号：US11754821
申请日：2007-05-29
申请人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.
摘要翻译：根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。逻辑芯片连接到电路板以向适配器卡提供功能。一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

2. 发明申请

US20080263391A1 Apparatus, System, and Method For Adapter Card Failover 审中-公开
标题翻译：用于适配器卡故障转移的设备，系统和方法
公开(公告)号：US20080263391A1
公开(公告)日：2008-10-23
申请号：US11738150
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/07
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
摘要翻译：公开了用于适配器卡故障切换的装置，系统和方法。开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡作为非所有者处理器复合体。非所有者处理器复合体管理第二个端口。检测模块检测第一处理器复杂的故障。设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。

3. 发明授权

US07596651B2 Multi-character adapter card 失效
标题翻译：多字符适配卡
公开(公告)号：US07596651B2
公开(公告)日：2009-09-29
申请号：US11754821
申请日：2007-05-29
申请人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F9/06
CPC分类号： G06F13/385
摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.
摘要翻译：根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。逻辑芯片连接到电路板以向适配器卡提供功能。一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

4. 发明申请

US20080263255A1 Apparatus, System, and Method For Adapter Card Failover 有权
公开(公告)号：US20080263255A1
公开(公告)日：2008-10-23
申请号：US11738142
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13/36
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

5. 发明授权

US07870417B2 Apparatus, system, and method for adapter card failover 有权
标题翻译：适配卡故障切换的装置，系统和方法
公开(公告)号：US07870417B2
公开(公告)日：2011-01-11
申请号：US11738142
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
摘要翻译：公开了用于适配器卡故障切换的装置，系统和方法。开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡，作为非所有者处理器复合体。非所有者处理器复合体管理第二个端口。检测模块检测第一处理器复杂的故障。设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。

6. 发明授权

US08782464B2 Method and system for using a standby server to improve redundancy in a dual-node data storage system 有权
公开(公告)号：US08782464B2
公开(公告)日：2014-07-15
申请号：US13076767
申请日：2011-03-31
申请人： Stephen L. Blinick , Scott A. Brewer , Yu-Cheng Hsu
发明人： Stephen L. Blinick , Scott A. Brewer , Yu-Cheng Hsu
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2046
摘要： A standby server, a first main server, and a second main server to control shared input/output (I/O) adapters in a storage system are provided. The standby server is in communication with the first main server and the second main server, and the storage system is configured to operate as a dual node active system. The standby server is activated in response to receiving a communication from the first main server of a fail mode of the second main server. Systems and physical computer storage media are also provided.

7. 发明授权

US08688914B2 Promotion of partial data segments in flash cache 有权
标题翻译：在Flash缓存中促进部分数据段
公开(公告)号：US08688914B2
公开(公告)日：2014-04-01
申请号：US13286465
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/0646 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0811 , G06F12/0862 , G06F12/0864 , G06F12/0871 , G06F12/0897 , G06F12/122 , G06F12/127 , G06F12/128 , G06F2212/1016 , G06F2212/154 , G06F2212/222 , G06F2212/283 , G06F2212/604 , G06F2212/702 , G06F2212/7201
摘要： For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage.
摘要翻译：为了以更有效的方式有效地在二级存储器中运行轨迹，对于与用于控制主存储器中的轨道的定时的顺序位一起使用的时间位，时间位和顺序位从主存储器传送到辅助存储器。时间位允许在辅助存储器上老化。

8. 发明授权

US08688913B2 Management of partial data segments in dual cache systems 有权
标题翻译：双缓存系统中部分数据段的管理
公开(公告)号：US08688913B2
公开(公告)日：2014-04-01
申请号：US13286454
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0868 , G06F12/0891 , G06F12/0897 , G06F12/126 , G06F2212/1021 , G06F2212/1041 , G06F2212/222 , G06F2212/283
摘要： For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.
摘要翻译：为了在由处理器具有较低和较高级别的高速缓存的计算存储环境中移动部分数据段，将包含部分数据段中的一个的整个数据段升级到较低级别和更高级别的高速缓存。整个数据段的请求数据被分割并定位在较高级缓存的降级队列的最近使用（MRU）部分。整个数据段的未请求的数据被分割并定位在较高级别的缓存的降级队列的最近最少使用（LRU）部分。未请求的数据被固定到位，直到整个数据段写入缓存的较低级别完成。

9. 发明申请

US20120191904A1 SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
标题翻译：用于写入累积和分析的二次高速缓存
公开(公告)号：US20120191904A1
公开(公告)日：2012-07-26
申请号：US13430613
申请日：2012-03-26
申请人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
发明人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0804 , G06F11/1008 , G06F11/1076 , G06F12/0866
摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.
摘要翻译：本文公开了一种高效地使用大型二级高速缓存的方法。在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。这些数据轨道可以包括经修改的数据和/或未修改的数据。该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。本文还公开了相应的计算机程序产品和装置。

10. 发明授权

US08898653B2 Non-disruptive code update of a single processor in a multi-processor computing system 有权
标题翻译：多处理器计算系统中单个处理器的无中断代码更新
公开(公告)号：US08898653B2
公开(公告)日：2014-11-25
申请号：US11769083
申请日：2007-06-27
申请人： Stephen L. Blinick , Chiahong Chen
发明人： Stephen L. Blinick , Chiahong Chen
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/44505 , G06F8/65 , G06F9/4401
摘要： Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.
摘要翻译：在多处理器系统中更新单个处理器的代码包括停止由系统中的第一处理器处理的事务，并且维护由系统中的第二处理器处理事务的处理。然后，第一处理器接收新的代码，并且终止在第一处理器上运行的操作系统，由此终止由第一处理器执行的所有进程和线程。开始执行第一处理器的自复位，并且禁用与第一处理器相关联的中断。只有与第一处理器完全相关联的系统资源被重置，并且与第一处理器相关联的存储器事务被禁用。将新代码的图像复制到与第一处理器相关联的存储器中，与第一处理器相关联的寄存器被复位，并且新代码由第一处理器引导。

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