专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06279078B1 Apparatus and method for synchronizing a cache mode in a dual controller, dual cache memory system operating in a plurality of cache modes 失效
标题翻译：用于同步双控制器中的高速缓存模式的装置和方法，以多个高速缓存模式操作的双缓存存储器系统
公开(公告)号：US06279078B1
公开(公告)日：2001-08-21
申请号：US08668512
申请日：1996-06-28
申请人： Stephen J. Sicola , Wayne H. Umland , Clark E. Lubbers , Susan G. Elkington
发明人： Stephen J. Sicola , Wayne H. Umland , Clark E. Lubbers , Susan G. Elkington
IPC分类号： G06F1216
CPC分类号： G06F11/2017 , G06F11/1666 , G06F11/20 , G06F11/2097 , G06F12/0802
摘要： An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.
摘要翻译：一种用于使计算机中的高速缓冲存储器系统中的高速缓存模式同步以保护高速缓存操作的装置和方法。高速缓冲存储器系统具有第一控制器和第二控制器以及两个高速缓存模块，并以多种高速缓存模式操作。高速缓存模式作为元数据存储在缓存模块中，由第一控制器检测以确定高速缓存模式。根据检测到的高速缓存模式来设置第一控制器中的锁定信号以设置第一控制器中的高速缓存模式状态。第二个控制器从第一个控制器复制缓存模式状态，以同步两个控制器处于相同的高速缓存模式状态。在第二控制器发生故障之后，第一控制器可以锁定对两个高速缓存的访问以恢复先前由第二控制器访问的数据。第二控制器从第一控制器重新启动并复制缓存模式状态，使得两个控制器在第二控制器发生故障之前返回到高速缓存模式状态。

2. 发明授权

US5974506A Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system 失效
标题翻译：在双缓存系统中启用镜像，非镜像和部分镜像缓存模式
公开(公告)号：US5974506A
公开(公告)日：1999-10-26
申请号：US671153
申请日：1996-06-28
申请人： Stephen J. Sicola , Wayne H. Umland , Thomas F. Fava , Clark E. Lubbers , Susan G. Elkington
发明人： Stephen J. Sicola , Wayne H. Umland , Thomas F. Fava , Clark E. Lubbers , Susan G. Elkington
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F12/0871 , G11C29/74 , G06F2212/1032 , G06F2212/1044 , G06F2212/286
摘要： A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.
摘要翻译：高速缓冲存储器系统在计算机的高速缓冲存储器系统中被启用为多个高速缓存模式之一。高速缓冲存储器系统具有第一控制器和两个高速缓存存储器，高速缓冲存储器被划分成每个高速缓冲存储器中具有两个象限的象限。第一控制器中的高速缓存模式检测器检测为高速缓冲存储器系统设置的镜像缓存模式。响应于检测到镜像高速缓存模式，第一控制器中的地址启用器使得能够访问第一对象限，每个高速缓冲存储器中的一个象限。第二个控制器遵循由高速缓存模式检测器设置的高速缓存模式，并具有地址启用器。第二控制器中的地址启用器使得能够以非镜像高速缓存模式访问一个高速缓冲存储器中的两个象限，并且响应于镜像缓存的检测，使得能够访问第二对象限，每个高速缓冲存储器中的一个象限模式由所述高速缓存模式检测器。

3. 发明授权

US06571324B1 Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system 失效
标题翻译：在镜像回写缓存系统中出现内存模块故障和数据重构的故障
公开(公告)号：US06571324B1
公开(公告)日：2003-05-27
申请号：US08883381
申请日：1997-06-26
申请人： Susan G. Elkington , Stephen J. Sicola , Wayne H. Umland
发明人： Susan G. Elkington , Stephen J. Sicola , Wayne H. Umland
IPC分类号： G06F1208
CPC分类号： G06F11/2082 , G11C29/74
摘要： A warmswap operation to replace modules in a mirrored cache system has been accomplished by disabling mirrored write operations in the cache system; testing the replacement memory module in the cache system; and restoring the mirrored data in the cache system. The restoring operation is accomplished by first quiescing write operations to stop writing data in the cache system not backed up in non-volatile data storage. Then data is copied from surviving memory modules to the replacement module, and the cooperative interaction of the surviving memory modules with the replacement memory module is validated. The validating operation verifies the cache modules are ready and the controllers are synchronized. After validation the quiesced write operations are un-quiesced, and mirrored-write operations for the cache system are enabled.
摘要翻译：通过禁用缓存系统中的镜像写入操作已经实现了用于替换镜像缓存系统中的模块的warmswap操作; 测试缓存系统中的替换内存模块; 并恢复缓存系统中的镜像数据。恢复操作通过首先停止写操作来停止在非易失性数据存储中未备份的缓存系统中写入数据来实现。然后将数据从幸存的存储器模块复制到替换模块，并且存活的存储器模块与替换存储器模块的协作交互被验证。验证操作验证缓存模块是否准备好并且控制器是同步的。在验证之后，静默写入操作是非静默的，并且缓存系统的镜像写操作被启用。

4. 发明授权

US5479413A Method for testing large memory arrays during system initialization 失效
标题翻译：在系统初始化期间测试大型存储器阵列的方法
公开(公告)号：US5479413A
公开(公告)日：1995-12-26
申请号：US254816
申请日：1994-06-06
申请人： Stephen J. Sicola , Wayne H. Umland
发明人： Stephen J. Sicola , Wayne H. Umland
IPC分类号： G11C29/02 , G11C29/08 , G11C29/10 , G01R31/28
CPC分类号： G11C29/02 , G11C29/08 , G11C29/10
摘要： An improved method for testing a large memory array of a digital computer system during system initialization or reset. First, the memory test method checks the whole memory array for addressing faults, and then a first portion of the memory array for both address line and data failures. While operational firmware is loaded into and begins to execute from the tested first portion, the remaining address locations of the array are tested in a background task. Beginning at the last address of the first portion, sequential portions of memory array are tested and released to the functional code as they have been tested.
摘要翻译：一种用于在系统初始化或复位期间测试数字计算机系统的大存储器阵列的改进方法。首先，存储器测试方法检查整个存储器阵列以寻址故障，然后检查存储器阵列的第一部分，用于地址线和数据故障。当操作固件被加载到测试的第一部分并且从测试的第一部分开始执行时，在后台任务中测试阵列的剩余地址位置。从第一部分的最后一个地址开始，存储器阵列的顺序部分经过测试并被发布到功能代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式