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1. 发明授权

US08949080B2 Methods of designing integrated circuits and systems thereof 有权
标题翻译：设计集成电路的方法及其系统
公开(公告)号：US08949080B2
公开(公告)日：2015-02-03
申请号：US12862991
申请日：2010-08-25
申请人： Kuo-Tsai Li , Paul Chang , Andy Chang
发明人： Kuo-Tsai Li , Paul Chang , Andy Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068 , G06F17/5081
摘要： A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.
摘要翻译：集成电路的设计方法包括执行集成电路的预布局仿真。使用从过程设计工具包（PDK）文件生成的网表执行预布局模拟。 PDK文件包括分配给多个设备的多个设备模型卡。多个器件包括具有至少一个与至少一个隔离阱相关联的寄生二极管的第一器件，该PDK文件包括至少一个寄生二极管的信息。生成对应于预布局仿真结果的集成电路的设计布局。

2. 发明授权

US07782073B2 High accuracy and universal on-chip switch matrix testline 有权
标题翻译：高精度和通用片上开关矩阵测试线
公开(公告)号：US07782073B2
公开(公告)日：2010-08-24
申请号：US11731444
申请日：2007-03-30
申请人： Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
发明人： Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2891 , H01L2924/0002 , H01L2924/00
摘要： A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.
摘要翻译：介绍了用于集成电路测试的测试线结构。该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。还提出了使用该测试线结构的方法。

3. 发明授权

US07113018B2 High voltage tolerant I/O circuit using native NMOS transistor for improved performance 有权
标题翻译：使用天然NMOS晶体管的高耐压I / O电路可提高性能
公开(公告)号：US07113018B2
公开(公告)日：2006-09-26
申请号：US10978019
申请日：2004-10-28
申请人： Kuo-Tsai Li , Chi-Chiang Lin
发明人： Kuo-Tsai Li , Chi-Chiang Lin
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.
摘要翻译：低电压电路和高电压电路之间的I / O电路包括开关器件，原生器件和栅极控制逻辑电路。开关装置响应于从低电压电路接收的数据输入信号向高电压电路提供输出信号。本地设备通过数据输入信号来控制开关设备的接通或断开状态。门控制逻辑电路在输出禁止模式和输出使能模式下工作。在输出禁止模式下，门控逻辑电路禁用本机器件，以防止漏电流通过。在输出使能模式下，栅极控制逻辑电路使本地器件能够通过数据输入信号而没有实质的电压降，从而提高了开关器件的切换速度。

4. 发明申请

US20080238453A1 High accuracy and universal on-chip switch matrix testline 有权
标题翻译：高精度和通用片上开关矩阵测试线
公开(公告)号：US20080238453A1
公开(公告)日：2008-10-02
申请号：US11731444
申请日：2007-03-30
申请人： Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
发明人： Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2891 , H01L2924/0002 , H01L2924/00
摘要： A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.
摘要翻译：介绍了用于集成电路测试的测试线结构。该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。还提出了使用该测试线结构的方法。

5. 发明申请

US20060091917A1 High voltage tolerant I/O circuit using native NMOS transistor for improved performance 有权
公开(公告)号：US20060091917A1
公开(公告)日：2006-05-04
申请号：US10978019
申请日：2004-10-28
申请人： Kuo-Tsai Li , Chi-Chiang Lin
发明人： Kuo-Tsai Li , Chi-Chiang Lin
IPC分类号： H03B1/00
CPC分类号： H03K19/00315
摘要： An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.

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