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1. 发明授权

US07428627B2 Method and apparatus for predicting values in a processor having a plurality of prediction modes 失效
标题翻译：用于预测具有多种预测模式的处理器中的值的方法和装置
公开(公告)号：US07428627B2
公开(公告)日：2008-09-23
申请号：US09750150
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F9/3844
摘要： A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.
摘要翻译：公开了一种具有多种预测模式的处理器的多模式预测器。预测模式用于预测非二进制值。预测器是包括每IP（“PIP”）表和下一个值表的多模式预测器。 PIP表包括多个PIP信息字段，下一个值表包括多个字段。多模式预测器还包括多种预测模式。处理器包括一组索引PIP表以提供有效信号的指令。处理器还包括用于该组指令的一组预测值。预测值的集合存储在PIP表和下一个值表中。根据有效信号在下一个值表中的命中/未命中条件，从PIP表或下一个值表中选择预测值。

2. 发明授权

US06438673B1 Correlated address prediction 有权
标题翻译：相关地址预测
公开(公告)号：US06438673B1
公开(公告)日：2002-08-20
申请号：US09475063
申请日：1999-12-30
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862 , G06F2212/6024
摘要： A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.
摘要翻译：具有相关地址预测器的微处理器，以及执行相关地址预测的方法。第一表存储器可以由多个缓冲器入口填充。每个缓冲器条目可以包括基于指令指针存储第一标签的第一缓冲区域和用于存储地址历史的第二缓冲区域。第二表存储器可以由多个链接条目填充。每个链接条目可以包括基于地址历史存储链接标签的第一链接字段和用于存储预测地址的第二链接字段。第一比较器可以与第一表存储器和指令指针输入通信。第二比较器可以与第一表存储器和第二表存储器通信。与第二表存储器通信的输出。

3. 发明授权

US06694421B2 Cache memory bank access prediction 有权
标题翻译：缓存存储器存取预测
公开(公告)号：US06694421B2
公开(公告)日：2004-02-17
申请号：US09474381
申请日：1999-12-29
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F1208
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个高速缓存存储体的处理器中的高速缓存存储体预测单元。高速缓存库预测单元具有接收指令的输入端口。高速缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个高速缓存组中的哪一个与该指令相关联。

4. 发明授权

US06631445B2 Cache structure for storing variable length data 有权
公开(公告)号：US06631445B2
公开(公告)日：2003-10-07
申请号：US10372194
申请日：2003-02-25
申请人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
发明人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0875 , G06F12/0886
摘要： A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

5. 发明授权

US06549987B1 Cache structure for storing variable length data 有权
公开(公告)号：US06549987B1
公开(公告)日：2003-04-15
申请号：US09713266
申请日：2000-11-16
申请人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
发明人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0875 , G06F12/0886
摘要： A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

6. 发明授权

US07644236B2 Memory cache bank prediction 失效
标题翻译：内存缓存库预测
公开(公告)号：US07644236B2
公开(公告)日：2010-01-05
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

7. 发明授权

US07757065B1 Instruction segment recording scheme 失效
标题翻译：指令段记录方案
公开(公告)号：US07757065B1
公开(公告)日：2010-07-13
申请号：US09708722
申请日：2000-11-09
申请人： Stephan J. Jourdan , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3808
摘要： In a front-end system for a processor, a recording scheme for instruction segments stores the instructions in reverse program order. Instruction segments may be traces, extended blocks or basic blocks. By storing the instructions in reverse program order, the instruction segment is easily extended to include additional instructions. The instruction segments may be extended without having to re-index tag arrays, pointers that associate instruction segments with other instruction segments.
摘要翻译：在用于处理器的前端系统中，用于指令段的记录方案以反向程序顺序存储指令。指令段可以是跟踪，扩展块或基本块。通过以反向程序顺序存储指令，指令段可以容易地扩展到包括附加指令。指令段可以被扩展，而不必重新索引标签数组，将指令段与其他指令段相关联的指针。

8. 发明授权

US06880063B2 Memory cache bank prediction 有权
标题翻译：内存缓存库预测
公开(公告)号：US06880063B2
公开(公告)日：2005-04-12
申请号：US10755017
申请日：2004-01-09
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

9. 发明申请

US20050262332A1 Method and system for branch target prediction using path information 审中-公开
标题翻译：使用路径信息进行分支目标预测的方法和系统
公开(公告)号：US20050262332A1
公开(公告)日：2005-11-24
申请号：US10404384
申请日：2003-03-31
申请人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
发明人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.
摘要翻译：一种用于预测微处理器当前指令的分支目标的系统和方法，该系统包括存储间接分支指令和路径寄存器的高速缓存器。通过路径寄存器和分支指令上的异或运算，在某些分支上更新路径寄存器，然后向寄存器添加一个或多个位。通过对当前指令地址和路径寄存器的一部分执行操作来对高速缓存进行索引; 返回的条目（如果有的话）可以用于预测当前指令的目标。

10. 发明申请

US20050132138A1 Memory cache bank prediction 失效
公开(公告)号：US20050132138A1
公开(公告)日：2005-06-16
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

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