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1. 发明授权

US10387312B2 System and method for event monitoring in cache coherence protocols without explicit invalidations 有权
公开(公告)号：US10387312B2
公开(公告)日：2019-08-20
申请号：US15108948
申请日：2015-01-02
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0815 , G06F12/084 , G06F12/128 , G06F13/16 , G06F12/0811 , G06F12/0817
摘要： Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.

2. 发明授权

US09274960B2 System and method for simplifying cache coherence using multiple write policies 有权
标题翻译：使用多个写策略简化缓存一致性的系统和方法
公开(公告)号：US09274960B2
公开(公告)日：2016-03-01
申请号：US13793521
申请日：2013-03-11
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084 , Y02D10/13
摘要： System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.
摘要翻译：具有本地/共享高速缓存层级的多核处理环境中的高速缓存一致性的系统和方法。该系统包括多个处理器核心，主存储器和与每个核心相关联的本地高速缓冲存储器，用于存储仅可由相关联的核心访问的高速缓存线。缓存行被分类为私有或共享。共享高速缓存存储器耦合到本地高速缓存存储器和用于存储高速缓存行的主存储器。内核遵循本地存储器的专用高速缓存行的回写，以及用于共享高速缓存行的共享内存的写入。本地高速缓存中的共享缓存行在内核写入时会进入暂时的脏状态。共享缓存行从一个瞬态脏到一个有效的状态，通过自启动的写入到共享内存。对共享内存的直写可以仅包括在瞬态脏状态下被修改的数据。

3. 发明授权

US10324861B2 Systems and methods for coherence in clustered cache hierarchies 有权
公开(公告)号：US10324861B2
公开(公告)日：2019-06-18
申请号：US15015274
申请日：2016-02-04
申请人： Alberto Ros , Stefanos Kaxiras
发明人： Alberto Ros , Stefanos Kaxiras
IPC分类号： G06F12/1045 , G06F12/084 , G06F12/0815 , G06F12/0897 , G06F12/0811 , G06F12/0891 , G06F12/0808
摘要： According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

4. 发明申请

US20130254488A1 SYSTEM AND METHOD FOR SIMPLIFYING CACHE COHERENCE USING MULTIPLE WRITE POLICIES 有权
标题翻译：使用多个写入策略简化高速缓存的系统和方法
公开(公告)号：US20130254488A1
公开(公告)日：2013-09-26
申请号：US13793521
申请日：2013-03-11
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084 , Y02D10/13
摘要： System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.
摘要翻译：具有本地/共享高速缓存层级的多核处理环境中的高速缓存一致性的系统和方法。该系统包括多个处理器核心，主存储器和与每个核心相关联的本地高速缓冲存储器，用于存储仅可由相关联的核心访问的高速缓存线。缓存行被分类为私有或共享。共享高速缓存存储器耦合到本地高速缓存存储器和用于存储高速缓存行的主存储器。内核遵循本地存储器的专用高速缓存行的回写，以及用于共享高速缓存行的共享内存的写入。本地高速缓存中的共享缓存行在内核写入时会进入暂时的脏状态。共享缓存行从一个瞬态脏到一个有效的状态，通过自启动的写入到共享内存。对共享内存的直写可以仅包括在瞬态脏状态下被修改的数据。

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