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1. 发明授权

US09274960B2 System and method for simplifying cache coherence using multiple write policies 有权
标题翻译：使用多个写策略简化缓存一致性的系统和方法
公开(公告)号：US09274960B2
公开(公告)日：2016-03-01
申请号：US13793521
申请日：2013-03-11
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084 , Y02D10/13
摘要： System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.
摘要翻译：具有本地/共享高速缓存层级的多核处理环境中的高速缓存一致性的系统和方法。该系统包括多个处理器核心，主存储器和与每个核心相关联的本地高速缓冲存储器，用于存储仅可由相关联的核心访问的高速缓存线。缓存行被分类为私有或共享。共享高速缓存存储器耦合到本地高速缓存存储器和用于存储高速缓存行的主存储器。内核遵循本地存储器的专用高速缓存行的回写，以及用于共享高速缓存行的共享内存的写入。本地高速缓存中的共享缓存行在内核写入时会进入暂时的脏状态。共享缓存行从一个瞬态脏到一个有效的状态，通过自启动的写入到共享内存。对共享内存的直写可以仅包括在瞬态脏状态下被修改的数据。

2. 发明授权

US10387312B2 System and method for event monitoring in cache coherence protocols without explicit invalidations 有权
公开(公告)号：US10387312B2
公开(公告)日：2019-08-20
申请号：US15108948
申请日：2015-01-02
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0815 , G06F12/084 , G06F12/128 , G06F13/16 , G06F12/0811 , G06F12/0817
摘要： Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.

3. 发明授权

US10324861B2 Systems and methods for coherence in clustered cache hierarchies 有权
公开(公告)号：US10324861B2
公开(公告)日：2019-06-18
申请号：US15015274
申请日：2016-02-04
申请人： Alberto Ros , Stefanos Kaxiras
发明人： Alberto Ros , Stefanos Kaxiras
IPC分类号： G06F12/1045 , G06F12/084 , G06F12/0815 , G06F12/0897 , G06F12/0811 , G06F12/0891 , G06F12/0808
摘要： According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

4. 发明申请

US20130254488A1 SYSTEM AND METHOD FOR SIMPLIFYING CACHE COHERENCE USING MULTIPLE WRITE POLICIES 有权
标题翻译：使用多个写入策略简化高速缓存的系统和方法
公开(公告)号：US20130254488A1
公开(公告)日：2013-09-26
申请号：US13793521
申请日：2013-03-11
申请人： Stefanos Kaxiras , Alberto Ros
发明人： Stefanos Kaxiras , Alberto Ros
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084 , Y02D10/13
摘要： System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.
摘要翻译：具有本地/共享高速缓存层级的多核处理环境中的高速缓存一致性的系统和方法。该系统包括多个处理器核心，主存储器和与每个核心相关联的本地高速缓冲存储器，用于存储仅可由相关联的核心访问的高速缓存线。缓存行被分类为私有或共享。共享高速缓存存储器耦合到本地高速缓存存储器和用于存储高速缓存行的主存储器。内核遵循本地存储器的专用高速缓存行的回写，以及用于共享高速缓存行的共享内存的写入。本地高速缓存中的共享缓存行在内核写入时会进入暂时的脏状态。共享缓存行从一个瞬态脏到一个有效的状态，通过自启动的写入到共享内存。对共享内存的直写可以仅包括在瞬态脏状态下被修改的数据。

5. 发明申请

US20060041769A1 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
公开(公告)号：US20060041769A1
公开(公告)日：2006-02-23
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/30
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.

6. 发明授权

US06983388B2 Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines 有权
标题翻译：用于通过使用去除相关联的高速缓存行的功率的定时器控制信号来减少高速缓冲存储器中的泄漏功率的方法和装置
公开(公告)号：US06983388B2
公开(公告)日：2006-01-03
申请号：US09865847
申请日：2001-05-25
申请人： Stefanos Kaxiras , Philip W. Diodato , Hubert Rae McLellan, Jr. , Girija Narlikar
发明人： Stefanos Kaxiras , Philip W. Diodato , Hubert Rae McLellan, Jr. , Girija Narlikar
IPC分类号： G06F1/32
CPC分类号： G11C5/143 , G11C11/417
摘要： A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset. When a cache line is later accessed after being powered down by the present invention, a cache miss is incurred while the cache line is again powered up and the data is obtained from the next level of the memory hierarchy.
摘要翻译：公开了一种用于减少高速缓冲存储器中的泄漏功率的方法和装置。缓存衰减技术被用于数据和指令高速缓存，这些高速缓存从预定义的时间间隔（称为衰减间隔）中去除未被访问的高速缓存行的功率。本发明的高速缓存线粒度允许显着降低泄漏功率，同时保持高速缓存的大部分性能。使用每次访问相应的高速缓存行时重置的定时器来维持衰减间隔。衰减间隔可以是固定的或可变的。一旦衰减间隔定时器超过指定的衰减间隔，就删除高速缓存行的电源。一旦去除了高速缓存线的电源，就允许数据和标签字段的内容衰减，并且与高速缓存行相关联的有效位被重置。当通过本发明关闭高速缓存行之后，高速缓存未命中，同时高速缓存行再次通电并且从存储器层级的下一级获得数据。

7. 发明授权

US06889293B1 Directory-based prediction methods and apparatus for shared-memory multiprocessor systems 失效
标题翻译：用于共享存储器多处理器系统的基于目录的预测方法和装置
公开(公告)号：US06889293B1
公开(公告)日：2005-05-03
申请号：US09591918
申请日：2000-06-09
申请人： Stefanos Kaxiras , Reginald Clifford Young
发明人： Stefanos Kaxiras , Reginald Clifford Young
IPC分类号： G06F12/06 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0817
摘要： A set of predicted readers are determined for a data block subject to a write request in a shared-memory multiprocessor system by first determining a current set of readers of the data block, and then generating the set of predicted readers based on the current set of readers and at least one additional set of readers representative of at least a portion of a global history of a directory associated with the data block. In one possible implementation, the set of predicted readers are generated by applying a function to the current set of readers and one or more additional sets of readers.
摘要翻译：在共享存储器多处理器系统中，通过首先确定数据块的当前读取器组，然后基于当前的一组读取器和至少一组额外的读取器，其代表与数据块相关联的目录的全局历史的至少一部分。在一个可能的实现中，通过将函数应用于当前读取器组和一个或多个另外的读取器组来生成预测读取器的集合。

8. 发明授权

US06665791B1 Method and apparatus for releasing functional units in a multithreaded VLIW processor 有权
标题翻译：用于释放多线程VLIW处理器中的功能单元的方法和装置
公开(公告)号：US06665791B1
公开(公告)日：2003-12-16
申请号：US09538669
申请日：2000-03-30
申请人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
发明人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
IPC分类号： G06F15163
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy. The functional unit release approach of the present invention allows the functional units that are not associated with a multiple-cycle instruction to be allocated to other threads while the blocked thread is waiting, thereby improving throughput of the multithreaded VLIW processor. Since the state is associated with each functional unit separately from the instruction issue unit, the functional units can be assigned to threads independently of the state of any one thread and its constituent instructions.
摘要翻译：公开了用于释放多线程超大指令字（VLIW）处理器中的功能单元的方法和装置。功能单元释放机构可以检索由于多个循环指令而导致的容量损失。本发明的功能单元释放机构允许将空闲功能单元重新分配给其他线程，从而提高工作效率。指令包被分配给功能单元，它们可以保持其状态，而与发行逻辑无关。每个功能单元具有关联的状态机（SM），其跟踪功能单元将被多周期指令占用的周期数。只要功能单元繁忙，功能单元就不会自动重新分配。指令完成后，即使分配给同一线程的其他功能单元仍然忙，功能单元也可以参与功能单元分配。本发明的功能单元释放方法允许在阻塞的线程等待时将不与多周期指令相关联的功能单元分配给其他线程，从而提高多线程VLIW处理器的吞吐量。由于状态与指令发布单元分开地与每个功能单元相关联，所以功能单元可以独立于任何一个线程的状态及其组成指令分配给线程。

9. 发明授权

US6061776A Multiple processor, distributed memory computer with out-of-order processing 有权
公开(公告)号：US6061776A
公开(公告)日：2000-05-09
申请号：US295836
申请日：1999-04-21
申请人： Douglas C. Burger , Stefanos Kaxiras , James R. Goodman
发明人： Douglas C. Burger , Stefanos Kaxiras , James R. Goodman
IPC分类号： G06F9/50 , G06F12/08 , G06F15/00
CPC分类号： G06F9/5016 , G06F12/0813 , G06F9/50
摘要： A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

10. 发明授权

US07472302B2 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
标题翻译：使用自适应基于时间的衰减来减少高速缓冲存储器中的泄漏功率的方法和装置
公开(公告)号：US07472302B2
公开(公告)日：2008-12-30
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/32
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.
摘要翻译：公开了一种自适应高速缓存衰减技术，其假设在将来不太可能访问这些高速缓存线，从而将高速缓存线路的功率从尚未被访问的可变时间间隔（称为高速缓存行衰减间隔）中移除。对于每个高速缓存线，衰减间隔可以增加或减小，以分别提高高速缓存性能或节省功率。初始建立高速缓存的默认衰减间隔，然后可以根据高速缓存衰减之后的高速缓存行的性能，为给定的高速缓存行调整默认衰减间隔。缓存衰减性能通过确定高速缓存行是否衰减太快来进行评估。如果缓存线被衰减并且再次需要相同的高速缓存内容，则高速缓存线被衰减太快，并且高速缓存行衰减间隔增加。如果缓存行被衰减并且然后访问高速缓存行以获得不同的高速缓存内容，则可以减少高速缓存行衰减间隔。当高速缓存行在衰减之后被访问时，产生高速缓存未命中，并且执行测试以通过确定是否再次访问相同的缓存内容来评估高速缓存衰减性能（例如，与后续访问相关联的地址是否为以前存储的内容的相同地址）。然后相应地调整缓存衰减间隔。

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