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1. 发明申请

US20060039197A1 Page buffer for a programmable memory device 有权
标题翻译：用于可编程存储器件的页缓冲器
公开(公告)号：US20060039197A1
公开(公告)日：2006-02-23
申请号：US11134158
申请日：2005-05-20
申请人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
发明人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.
摘要翻译：提供了一种用于电可编程存储器的页缓冲器，其包括形成多个存储器页的多个存储单元。页面缓冲器包括用于至少临时存储从或将要写入所选存储器页的存储器单元的数据的寄存器。寄存器包括多个锁存器和多个缓冲器元件。每个锁存器耦合到至少一个信号线，用于传送存储在锁存器中的数据位。每个缓冲元件将锁存器中相应一个的输出与信号线分离，缓冲元件根据存储在相应锁存器中的数据位来驱动信号线。还提供了一种将数据从寄存器传送到电可编程存储器中的信号线的方法。

2. 发明申请

US20060007774A1 Page buffer circuit and method for a programmable memory device 有权
公开(公告)号：US20060007774A1
公开(公告)日：2006-01-12
申请号：US11166354
申请日：2005-06-24
申请人： Stefano Zanardi , Giulio Martinozzi
发明人： Stefano Zanardi , Giulio Martinozzi
IPC分类号： G11C8/00
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/14
摘要： A page buffer for an electrically programmable memory includes a plurality of storage units, each comprising a first latch and a second latch. Input switching means loads into the latch the data bit to be written and to be temporarily stored. The input switching means has an input terminal connected to the respective data line for receiving a set voltage provided therethrough. The input switching means provides the set voltage to the first or second input/output terminals of the latch depending on the data bit to be written. An output switch device transfers onto the respective data line the read data bit temporarily stored into the latch and has a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

3. 发明授权

US07567456B2 Page buffer circuit and method for a programmable memory device 有权
标题翻译：页面缓冲电路和可编程存储器件的方法
公开(公告)号：US07567456B2
公开(公告)日：2009-07-28
申请号：US11166354
申请日：2005-06-24
申请人： Stefano Zanardi , Giulio Martinozzi
发明人： Stefano Zanardi , Giulio Martinozzi
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/14
摘要： A page buffer for an electrically programmable memory includes a plurality of storage units, each comprising a first latch and a second latch. Input switching means loads into the latch the data bit to be written and to be temporarily stored. The input switching means has an input terminal connected to the respective data line for receiving a set voltage provided therethrough. The input switching means provides the set voltage to the first or second input/output terminals of the latch depending on the data bit to be written. An output switch device transfers onto the respective data line the read data bit temporarily stored into the latch and has a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.
摘要翻译：用于电可编程存储器的页面缓冲器包括多个存储单元，每个存储单元包括第一锁存器和第二锁存器。输入切换意味着将要写入并临时存储的数据位加载到锁存器中。输入切换装置具有连接到相应数据线的输入端，用于接收从其提供的设定电压。输入切换装置根据要写入的数据位来向锁存器的第一或第二输入/输出端提供设定电压。输出开关装置将相应的数据线传送到临时存储到锁存器中的读数据位，并且具有耦合到锁存器的第一和第二输入/输出端之一的第一端，连接到相应数据线的第二端和接收输出控制信号的控制终端。

4. 发明授权

US07298650B2 Page buffer for a programmable memory device 有权
标题翻译：用于可编程存储器件的页缓冲器
公开(公告)号：US07298650B2
公开(公告)日：2007-11-20
申请号：US11134158
申请日：2005-05-20
申请人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
发明人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
IPC分类号： G11C16/04 , G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C16/26
摘要： A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.
摘要翻译：提供了一种用于电可编程存储器的页面缓冲器，其包括形成多个存储器页面的多个存储器单元。页面缓冲器包括用于至少临时存储从或将要写入所选存储器页的存储器单元的数据的寄存器。寄存器包括多个锁存器和多个缓冲器元件。每个锁存器耦合到至少一个信号线，用于传送存储在锁存器中的数据位。每个缓冲元件将锁存器中相应一个的输出与信号线分离，缓冲元件根据存储在相应锁存器中的数据位来驱动信号线。还提供了一种将数据从寄存器传送到电可编程存储器中的信号线的方法。

5. 发明授权

US07471576B2 Method of transferring data in an electrically programmable memory 有权
标题翻译：在电可编程存储器中传送数据的方法
公开(公告)号：US07471576B2
公开(公告)日：2008-12-30
申请号：US11931497
申请日：2007-10-31
申请人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
发明人： Osama Khouri , Stefano Zanardi , Giulio Martinozzi
IPC分类号： G11C7/10 , G11C11/34 , G11C16/04 , G11C8/00
CPC分类号： G11C16/26
摘要： A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.
摘要翻译：提供了一种用于在包括形成存储器页面的存储器单元的存储器中传送数据的方法，以及包括寄存器的页缓冲器，其中信号线选择性地将存储在寄存器中的数据传送到所选择的一个存储器页的存储器单元，存储器的输出接口。从存储器页面选择的一个存储器单元的存储单元中读取或写入的数据至少暂时存储在寄存器中，缓冲寄存器的输出，以使寄存器的输出与信号线分离。信号线包括各自耦合到耦合到存储器的输出接口的一些存储器单元和数据线的位线。缓冲包括根据存储在寄存器中的数据字选择性地驱动位线或数据线。

6. 发明申请

US20080065823A1 METHOD OF TRANSFERRING DATA IN AN ELECTRICALLY PROGRAMMABLE MEMORY 有权
标题翻译：在电子可编程存储器中传输数据的方法
公开(公告)号：US20080065823A1
公开(公告)日：2008-03-13
申请号：US11931497
申请日：2007-10-31
申请人： OSAMA KHOURI , Stefano Zanardi , Giulio Martinozzi
发明人： OSAMA KHOURI , Stefano Zanardi , Giulio Martinozzi
IPC分类号： G06F12/00
CPC分类号： G11C16/26
摘要： A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.
摘要翻译：提供了一种用于在包括形成存储器页面的存储器单元的存储器中传送数据的方法，以及包括寄存器的页缓冲器，其中信号线选择性地将存储在寄存器中的数据传送到所选择的一个存储器页的存储器单元，存储器的输出接口。从存储器页面选择的一个存储器单元的存储单元中读取或写入的数据至少暂时存储在寄存器中，缓冲寄存器的输出，以使寄存器的输出与信号线分离。信号线包括各自耦合到耦合到存储器的输出接口的一些存储器单元和数据线的位线。缓冲包括根据存储在寄存器中的数据字选择性地驱动位线或数据线。

7. 发明授权

US08724361B2 DMA architecture for NAND-type flash memory 失效
标题翻译： NAND型闪存的DMA架构
公开(公告)号：US08724361B2
公开(公告)日：2014-05-13
申请号：US13364971
申请日：2012-02-02
申请人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
发明人： Mauro Pagliato , Giulio Martinozzi , Francesco Pessina
IPC分类号： G11C5/06
CPC分类号： G11C7/1039 , G11C16/00 , G11C16/0483 , G11C29/1201 , G11C29/50004 , G11C2029/5006
摘要： A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.
摘要翻译：一种设备包括非易失性存储器阵列，包括多个位线的静态随机存取存储器（SRAM）阵列，其包括彼此配对的第一和第二位线以及焊盘。第一电路耦合在非易失性存储器阵列与第一和第二位线之间，并与SRAM阵列接口。第二电路耦合在焊盘和第一和第二位线之间，并与SRAM阵列的接口连接。控制电路执行第一操作以经由SRAM阵列和第一和第二电路访问非易失性存储器阵列，并且通过产生通过第一和第二电路中的至少一个产生从焊盘连接到非易失性存储器阵列的电路来执行第二操作 SRAM阵列的第二位线，而不插入第一和第二电路中的至少一个。

8. 发明授权

US08391086B2 Mask-write apparatus for a SRAM cell 失效
标题翻译：用于SRAM单元的掩模写装置
公开(公告)号：US08391086B2
公开(公告)日：2013-03-05
申请号：US13040766
申请日：2011-03-04
申请人： Giulio Martinozzi , Mauro Pagliato
发明人： Giulio Martinozzi , Mauro Pagliato
IPC分类号： G11C7/00
CPC分类号： G11C7/1009 , G11C11/419
摘要： Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
摘要翻译：本文公开了一种包括SRAM单元，与SRAM单元耦合的一对位线的装置，响应于待写入数据的第一和第二输出节点产生真实和互补数据信号的写入电路，第一传输晶体管耦合在所述一对位线之一和所述写入电路的所述第一输出节点之间;耦合在所述一对位线中的另一个和所述写入电路的所述第二输出节点之间的第二传输晶体管; 以及掩模写入电路，被配置为在写入操作中使第一和第二通过晶体管都导通，并且在写入掩模操作中使第一和第二通过晶体管中的一个或多个不导通。

9. 发明申请

US20130010543A1 MEMORY DEVICE HAVING SWITCH PROVIDING VOLTAGE TO BIT LINE 失效
标题翻译：具有向位线提供电压的开关的存储器件
公开(公告)号：US20130010543A1
公开(公告)日：2013-01-10
申请号：US13176337
申请日：2011-07-05
申请人： Giulio Martinozzi
发明人： Giulio Martinozzi
IPC分类号： G11C29/00 , G11C5/14 , G11C7/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.
摘要翻译：一种存储器件，其中电路读取单元条件。端子通过开关向电路的位线提供电压。当从终端提供的电压不超过阈值时，电路输出并使能存储第一逻辑值。当从终端提供的电压超过阈值时，电路输出并使能存储第二逻辑值。输出和存储发生在电池和电路之间没有电连接的情况下。开关提供从端子提供的电压到电路的位线。电压从不超过阈值的值增加到超过阈值的值。

10. 发明申请

US20120224439A1 MASK-WRITE APPARATUS FOR A SRAM CELL 失效
标题翻译：用于SRAM单元的MASK-WRITE设备
公开(公告)号：US20120224439A1
公开(公告)日：2012-09-06
申请号：US13040766
申请日：2011-03-04
申请人： Giulio Martinozzi , Mauro Pagliato
发明人： Giulio Martinozzi , Mauro Pagliato
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1009 , G11C11/419
摘要： Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
摘要翻译：本文公开了一种包括SRAM单元，与SRAM单元耦合的一对位线的装置，响应于待写入数据的第一和第二输出节点产生真实和互补数据信号的写入电路，第一传输晶体管耦合在所述一对位线之一和所述写入电路的所述第一输出节点之间;耦合在所述一对位线中的另一个和所述写入电路的所述第二输出节点之间的第二传输晶体管; 以及掩模写入电路，被配置为在写入操作中使第一和第二通过晶体管都导通，并且在写入掩模操作中使第一和第二通过晶体管中的一个或多个不导通。

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