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1. 发明授权

US5299198A Method and apparatus for exploitation of voice inactivity to increase the capacity of a time division multiple access radio communications system 失效
标题翻译：利用语音不活动的方法和装置，以增加时分多址无线电通信系统的容量
公开(公告)号：US5299198A
公开(公告)日：1994-03-29
申请号：US622232
申请日：1990-12-06
申请人： Stanley E. Kay , John E. Corrigan, III , Daniel Wendling , Ashok Mehta , Michael Parr
发明人： Stanley E. Kay , John E. Corrigan, III , Daniel Wendling , Ashok Mehta , Michael Parr
IPC分类号： G10L19/00 , H04B7/26 , H04J3/17 , H04L12/28 , H04L12/56 , H04W28/06 , H04W72/04 , H04J3/16
CPC分类号： H04W72/044 , G10L19/012 , H04B7/26 , H04B7/2643 , H04J3/172 , H04W28/06 , H04W72/0406
摘要： A mobile telephone system multiplexes plural voice traffic channels on a single carrier using a TDMA protocol. The capacity of the mobile telephone system is increased by assigning voice traffic capacity, not on a conversation basis, but on a speech spurt basis. In order to avoid compromising the voice transmission capacity, control signals (for the allocation and deallocation of both forward and reverse traffic channels) are sent using multiple diversity, i.e. both time and frequency. In addition, to increase the number of available control channels, a control channel comprises a sub-divided portion of an otherwise equivalent voice traffic slot. For reverse allocation requests, which are transmitted over a contention access channel, power diversity is used in addition to time and frequency diversity.
摘要翻译：移动电话系统使用TDMA协议在单个载波上复用多个语音业务信道。移动电话系统的容量通过分配语音流量来提高，而不是在对话的基础上，而是基于语音突发。为了避免损害语音传输容量，使用多个分集即时间和频率来发送控制信号（用于正向和反向业务信道的分配和解除分配）。此外，为了增加可用控制信道的数量，控制信道包括另外等价的话音业务时隙的分分割部分。对于通过竞争接入信道发送的反向分配请求，除了时间和频率分集之外还使用功率分集。

2. 发明授权

US08966419B2 System and method for testing stacked dies 有权
标题翻译：堆叠模具测试系统和方法
公开(公告)号：US08966419B2
公开(公告)日：2015-02-24
申请号：US13546037
申请日：2012-07-11
申请人： Sandeep Kumar Goel , Ashok Mehta
发明人： Sandeep Kumar Goel , Ashok Mehta
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G01R31/318513
摘要： Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.
摘要翻译：公开了用于测试一堆管芯和插入修复电路的系统和方法，该修复电路在使能时补偿管芯堆叠中的延迟缺陷，特别是在缺陷位于管芯间数据传输路径中的情况。确定晶片内和模间松弛值以确定模具堆叠中的哪个模具或模具将从插入修复电路中受益。

3. 发明授权

US08402404B1 Stacked die interconnect validation 有权
标题翻译：堆叠芯片互连验证
公开(公告)号：US08402404B1
公开(公告)日：2013-03-19
申请号：US13298541
申请日：2011-11-17
申请人： Ashok Mehta , Stanley John , Kai-Yuan Ting , Sandeep Kumar Goel , Chao-Yang Yeh
发明人： Ashok Mehta , Stanley John , Kai-Yuan Ting , Sandeep Kumar Goel , Chao-Yang Yeh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/50 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A system includes an automated place and route tool to generate a layout of an integrated circuit (IC) die based on a gate level circuit description. A machine readable persistent storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second IC dies, respectively, and a second portion encoded with a second gate level description of the plurality of circuit patterns received from the tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented verification module is provided for comparing the first and second gate level descriptions and outputting an error report if the second gate level description has an error. The verification module outputs a verified second gate-level description of the first and second circuit patterns.
摘要翻译：一种系统包括基于门级电路描述产生集成电路（IC）裸片的布局的自动放置和布线工具。机器可读永久存储介质分别包括第一部分，第一部分被编码为将分别形成在第一和第二IC管芯上的第一和第二电路图案的第一栅极级描述，以及用多个第二栅极电平描述编码的第二部分从工具接收的电路图案。第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。提供了一种处理器实现的验证模块，用于比较第一和第二门级描述，并且如果第二门级描述具有错误则输出错误报告。验证模块输出第一和第二电路图案的验证的第二门级描述。

4. 发明申请

US20130198706A1 FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) 有权
标题翻译：从变更转换（VCD）到通用验证方法（UVM）的格式转换
公开(公告)号：US20130198706A1
公开(公告)日：2013-08-01
申请号：US13362415
申请日：2012-01-31
申请人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.
摘要翻译：公开了一种用于多管芯3D IC中的管芯的功能验证和/或模拟的系统和方法。该系统和方法包括将体现为值变更转储的I / O跟踪转换为一个或多个通用验证方法对象。这种转换有助于识别和修复死亡中包含的问题。

5. 发明申请

US20130193980A1 SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs 有权
标题翻译：用于多模3D IC功能验证的系统和方法
公开(公告)号：US20130193980A1
公开(公告)日：2013-08-01
申请号：US13359921
申请日：2012-01-27
申请人： Stanley JOHN , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley JOHN , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

6. 发明授权

US09015649B2 Method and apparatus for electronic system model generation 有权
标题翻译：电子系统模型生成的方法和装置
公开(公告)号：US09015649B2
公开(公告)日：2015-04-21
申请号：US12838577
申请日：2010-07-19
申请人： Ashok Mehta
发明人： Ashok Mehta
IPC分类号： G06F9/44 , G06F9/45 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F2217/86
摘要： A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model.
摘要翻译：公开了发送数据的方法。系统级芯片（SoC）的至少一个系统块在第一和第二未定义功能模型中的未定义的功能级别被建模。至少一个系统块系统块的第一和第二事务级（TL）模型分别使用第一和第二未定义的功能模型在事务级（TL）建模。第一和第二周期精确（CA）模型分别使用第一和第二TL模型在循环准确（CA）级别建模。数据从第一个未定义的功能模型传输到第一个CA模型，从第一个CA模型到第二个CA模型，经由CA总线，从第二个CA模型传输到第二个未定义的功能模型。

7. 发明授权

US08972918B2 System and method for functional verification of multi-die 3D ICs 有权
标题翻译：多芯片3D IC的功能验证系统和方法
公开(公告)号：US08972918B2
公开(公告)日：2015-03-03
申请号：US13359921
申请日：2012-01-27
申请人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

8. 发明授权

US5678180A Communication system and method providing dispatch and cellular interconnect communications 失效
标题翻译：提供调度和蜂窝互连通信的通信系统和方法
公开(公告)号：US5678180A
公开(公告)日：1997-10-14
申请号：US480727
申请日：1995-06-07
申请人： Ashok Mehta , Lin-nan Lee , Jim Hobza , Stanley Kay
发明人： Ashok Mehta , Lin-nan Lee , Jim Hobza , Stanley Kay
IPC分类号： H04W16/24 , H04W84/08 , H04Q7/00 , H04Q9/00
CPC分类号： H04W16/24 , H04W84/08
摘要： A dispatch system and a cellular interconnect system are combined to form a single system in which dispatch and interconnect communications are made with use of common system equipment. Different system configurations are employed according to the number of cells in the system to minimize loss of cellular interconnect capacity arising from dispatch communication operations.
摘要翻译：调度系统和蜂窝互连系统被组合以形成使用公共系统设备进行调度和互连通信的单个系统。根据系统中的小区数目采用不同的系统配置，以最小化由调度通信操作引起的蜂窝互连容量的损失。

9. 发明授权

US10061374B2 Dynamic frequency scaling 有权
公开(公告)号：US10061374B2
公开(公告)日：2018-08-28
申请号：US13414201
申请日：2012-03-07
申请人： Kai-Yuan Ting , Ashok Mehta , Sandeep Kumar Goel , Stanley John
发明人： Kai-Yuan Ting , Ashok Mehta , Sandeep Kumar Goel , Stanley John
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F1/32
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

10. 发明授权

US08578309B2 Format conversion from value change dump (VCD) to universal verification methodology (UVM) 有权
标题翻译：从变更转储（VCD）到通用验证方法（UVM）的格式转换
公开(公告)号：US08578309B2
公开(公告)日：2013-11-05
申请号：US13362415
申请日：2012-01-31
申请人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.
摘要翻译：公开了一种用于多管芯3D IC中的管芯的功能验证和/或模拟的系统和方法。该系统和方法包括将体现为值变更转储的I / O跟踪转换为一个或多个通用验证方法对象。这种转换有助于识别和修复死亡中包含的问题。

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