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1. 发明授权

US08972918B2 System and method for functional verification of multi-die 3D ICs 有权
标题翻译：多芯片3D IC的功能验证系统和方法
公开(公告)号：US08972918B2
公开(公告)日：2015-03-03
申请号：US13359921
申请日：2012-01-27
申请人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

2. 发明申请

US20130198706A1 FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) 有权
标题翻译：从变更转换（VCD）到通用验证方法（UVM）的格式转换
公开(公告)号：US20130198706A1
公开(公告)日：2013-08-01
申请号：US13362415
申请日：2012-01-31
申请人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.
摘要翻译：公开了一种用于多管芯3D IC中的管芯的功能验证和/或模拟的系统和方法。该系统和方法包括将体现为值变更转储的I / O跟踪转换为一个或多个通用验证方法对象。这种转换有助于识别和修复死亡中包含的问题。

3. 发明申请

US20130193980A1 SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs 有权
标题翻译：用于多模3D IC功能验证的系统和方法
公开(公告)号：US20130193980A1
公开(公告)日：2013-08-01
申请号：US13359921
申请日：2012-01-27
申请人： Stanley JOHN , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley JOHN , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

4. 发明授权

US08402404B1 Stacked die interconnect validation 有权
标题翻译：堆叠芯片互连验证
公开(公告)号：US08402404B1
公开(公告)日：2013-03-19
申请号：US13298541
申请日：2011-11-17
申请人： Ashok Mehta , Stanley John , Kai-Yuan Ting , Sandeep Kumar Goel , Chao-Yang Yeh
发明人： Ashok Mehta , Stanley John , Kai-Yuan Ting , Sandeep Kumar Goel , Chao-Yang Yeh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/50 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A system includes an automated place and route tool to generate a layout of an integrated circuit (IC) die based on a gate level circuit description. A machine readable persistent storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second IC dies, respectively, and a second portion encoded with a second gate level description of the plurality of circuit patterns received from the tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented verification module is provided for comparing the first and second gate level descriptions and outputting an error report if the second gate level description has an error. The verification module outputs a verified second gate-level description of the first and second circuit patterns.
摘要翻译：一种系统包括基于门级电路描述产生集成电路（IC）裸片的布局的自动放置和布线工具。机器可读永久存储介质分别包括第一部分，第一部分被编码为将分别形成在第一和第二IC管芯上的第一和第二电路图案的第一栅极级描述，以及用多个第二栅极电平描述编码的第二部分从工具接收的电路图案。第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。提供了一种处理器实现的验证模块，用于比较第一和第二门级描述，并且如果第二门级描述具有错误则输出错误报告。验证模块输出第一和第二电路图案的验证的第二门级描述。

5. 发明授权

US10061374B2 Dynamic frequency scaling 有权
公开(公告)号：US10061374B2
公开(公告)日：2018-08-28
申请号：US13414201
申请日：2012-03-07
申请人： Kai-Yuan Ting , Ashok Mehta , Sandeep Kumar Goel , Stanley John
发明人： Kai-Yuan Ting , Ashok Mehta , Sandeep Kumar Goel , Stanley John
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F1/32
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

6. 发明授权

US08578309B2 Format conversion from value change dump (VCD) to universal verification methodology (UVM) 有权
标题翻译：从变更转储（VCD）到通用验证方法（UVM）的格式转换
公开(公告)号：US08578309B2
公开(公告)日：2013-11-05
申请号：US13362415
申请日：2012-01-31
申请人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Ashok Mehta , Stanley John , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.
摘要翻译：公开了一种用于多管芯3D IC中的管芯的功能验证和/或模拟的系统和方法。该系统和方法包括将体现为值变更转储的I / O跟踪转换为一个或多个通用验证方法对象。这种转换有助于识别和修复死亡中包含的问题。

7. 发明申请

US20130238309A1 DYNAMIC FREQUENCY SCALING 审中-公开
标题翻译：动态频率范围
公开(公告)号：US20130238309A1
公开(公告)日：2013-09-12
申请号：US13414201
申请日：2012-03-07
申请人： Kai-Yuan TING , Ashok Mehta , Sandeep Kumar Goel , Stanley John
发明人： Kai-Yuan TING , Ashok Mehta , Sandeep Kumar Goel , Stanley John
IPC分类号： G06F17/50
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.
摘要翻译：一种用于电子系统级（ESL）上的动态频率缩放（DFS）的方法。该方法可以在虚拟环境中运行，并且基于第一事务时间和第二事务时间动态地缩放虚拟组件的频率。

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