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    • 1. 发明申请
      US20060190908A1 Coding of FPGA and standard cell logic in a tiling structure 审中-公开
    • Coding of FPGA and standard cell logic in a tiling structure
    • FPGA和标准单元逻辑在平铺结构中的编码
    • US20060190908A1
    • 2006-08-24
    • US11375891
    • 2006-03-15
    • Stanislav Bajuk , Jack Smith , Sebastian Ventrone
    • Stanislav Bajuk , Jack Smith , Sebastian Ventrone
    • G06F17/50
    • G06F17/5045 , G06F17/5068
    • A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.
    • 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明申请
      US20080030226A1 FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
    • FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    • FPGA电源到已知的功能状态
    • US20080030226A1
    • 2008-02-07
    • US11869921
    • 2007-10-10
    • Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
    • Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
    • H03K19/173
    • H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
    • A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
    • 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20070075733A1 FPGA POWERUP TO KNOWN FUNCTIONAL STATE 有权
    • FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    • FPGA电源到已知的功能状态
    • US20070075733A1
    • 2007-04-05
    • US11162997
    • 2005-09-30
    • Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
    • Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
    • H03K19/177
    • H03K19/17776 , H03K19/17732 , H03K19/17756 , H03K19/17772
    • A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
    • 包括基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）装置。 非基于编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而节省加电时的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和齐平扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20050125749A1 METHOD OF SELECTIVELY BUILDING REDUNDANT LOGIC STRUCTURES TO IMPROVE FAULT TOLERANCE 失效
    • METHOD OF SELECTIVELY BUILDING REDUNDANT LOGIC STRUCTURES TO IMPROVE FAULT TOLERANCE
    • 选择性建立冗余逻辑结构以提高容错能力的方法
    • US20050125749A1
    • 2005-06-09
    • US10707323
    • 2003-12-05
    • Kenneth Goodnow , Clarence Ogilvie , Jack Smith , Sebastian Ventrone
    • Kenneth Goodnow , Clarence Ogilvie , Jack Smith , Sebastian Ventrone
    • G06F17/50
    • G06F17/5045 , G06F11/18
    • A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.
    • 用于指定特定逻辑功能作为容错的寄存器传输级（RTL）的新硬件描述语言（HDL）扩展以及为容错逻辑功能实现故障冗余方案的方法。 代码（20）以RTL写入VHDL，并包括将操作符“FT”添加到某些逻辑功能的指令。 包括FT操作员的逻辑功能被认为是关键功能，即容错。 通过包括FT操作员，逻辑综合工具被提醒已被指定为容错的功能。 因此，预编程的逻辑综合工具使得IC的设计包括用于包括FT操作员的逻辑功能的故障冗余方案（30）。 故障冗余方案（30）包括逻辑功能的三个副本，即复制A（32），复制B（34）和复制C（36）以及多数选民38。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明申请
      US20050010888A1 AUTOMATIC LATCH COMPRESSION/REDUCTION 有权
    • AUTOMATIC LATCH COMPRESSION/REDUCTION
    • 自动锁紧/降低
    • US20050010888A1
    • 2005-01-13
    • US10604279
    • 2003-07-08
    • Jack Smith , Sebastian Ventrone
    • Jack Smith , Sebastian Ventrone
    • G06F9/45 , G06F17/50
    • G06F17/5045
    • The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other. The invention determines whether latches transition during the same clock cycle by running a simulation of an initial physical design and recording the latches that transition during each clock cycle. The invention also determines whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle. The foregoing process of eliminating redundant latches comprises replacing at least two latches with a single latch. The process of eliminating redundant latches produces a revised physical design, and the invention tests the revised physical design to determine whether the revised physical design performs as expected.
    • 本公开提供了一种设计具有锁存器的集成电路的方法。 本发明首先准备逻辑设备和锁存器的逻辑设计，然后基于逻辑设计将逻辑器件和锁存器定位在集成电路内，从而创建物理设计。 在创建物理设计的过程中，本发明通过组合在同一时钟周期内不转换的锁存器来消除冗余锁存器，与相同逻辑功能不相关的锁存器，处于相同时钟域的锁存器和锁存器 在彼此的给定物理接近度内。 本发明通过运行初始物理设计的模拟并且记录在每个时钟周期期间转换的锁存器来确定锁存器是否在同一时钟周期内转变。 本发明还确定在相同时钟周期期间不转换的锁存器的转换之间是否存在适当的定时松弛。 消除冗余锁存器的上述过程包括用单个锁存器替换至少两个锁存器。 消除冗余锁存器的过程产生修改的物理设计，并且本发明测试修改的物理设计以确定修改后的物理设计是否按预期执行。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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