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1. 发明授权

US07080111B2 Floating point multiply accumulator 失效
公开(公告)号：US07080111B2
公开(公告)日：2006-07-18
申请号：US09873557
申请日：2001-06-04
申请人： Amaresh Pangal , Dinesh Somasekhar , Shekhar Y. Borkar , Sriram R. Vangal
发明人： Amaresh Pangal , Dinesh Somasekhar , Shekhar Y. Borkar , Sriram R. Vangal
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936
摘要： A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

2. 发明授权

US06889241B2 Floating point adder 失效
标题翻译：浮点加法器
公开(公告)号：US06889241B2
公开(公告)日：2005-05-03
申请号：US09873721
申请日：2001-06-04
申请人： Amaresh Pangal , Dinesh Somasekhar , Sriram R. Vangal , Yatin V. Hoskote
发明人： Amaresh Pangal , Dinesh Somasekhar , Sriram R. Vangal , Yatin V. Hoskote
IPC分类号： G06F7/42 , G06F7/485 , G06F7/50
CPC分类号： G06F7/485 , G06F2207/3868
摘要： A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.
摘要翻译：浮点加法器电路包括指数路径和尾数路径。指数路径包括比较两个三位指数的比较器。两个指数各自递增，并且从两个原始指数中的一个或递增指数中的一个中选择合成指数。尾数路径包括加法器，以及加法器旁路路径，以选择其中之一代替执行加法。尾数路径还包括恒定移位器，有条件地将尾数向右移动三十二位。

3. 发明授权

US06459316B1 Flip flop circuit 失效
标题翻译：触发电路
公开(公告)号：US06459316B1
公开(公告)日：2002-10-01
申请号：US09733216
申请日：2000-12-08
申请人： Sriram R. Vangal , Dinesh Somasekhar
发明人： Sriram R. Vangal , Dinesh Somasekhar
IPC分类号： H03K3289
CPC分类号： H03K3/0372 , H03K3/356121
摘要： A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.
摘要翻译：具有互补输出的双轨触发器包括具有嵌入式逻辑的主级，感测级和一个或多个从动级。触发器工作在预充电状态和评估状态。在时钟信号为低电平的预充电状态期间，触发器将内部保持器节点预充电到高电平。当时钟信号变为高电平时，触发器进入评估状态，并且内部保持器节点之一评估为低值。感觉阶段感知内部维护者节点评估为零，并将其驱动到零更快。从站阶段在评估状态期间反映内部守门员节点的状态，并在预充电状态期间维持其状态。

4. 发明授权

US06701339B2 Pipelined compressor circuit 有权
标题翻译：流水线压缩机电路
公开(公告)号：US06701339B2
公开(公告)日：2004-03-02
申请号：US09733482
申请日：2000-12-08
申请人： Sriram R. Vangal , Dinesh Somasekhar
发明人： Sriram R. Vangal , Dinesh Somasekhar
IPC分类号： G06F752
CPC分类号： G06F9/38 , G06F7/607 , G06F9/3875 , G06F2207/3884
摘要： A pipelined four-to-two compressor includes sequential elements with embedded logic. One sequential element is a flip flop with complementary outputs that includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. Keeper nodes can also be dynamic flip flop outputs that pre-charge each clock cycle. Another flip flop with embedded logic receives the dynamic output, applies further logic, and provides a static output.
摘要翻译：流水线四对二压缩机包括具有嵌入式逻辑的顺序元件。一个顺序元件是具有互补输出的触发器，其包括具有嵌入逻辑的主级，感测级和一个或多个从级。触发器工作在预充电状态和评估状态。在时钟信号为低电平的预充电状态期间，触发器将内部保持器节点预充电到高电平。当时钟信号变为高电平时，触发器进入评估状态，并且内部保持器节点之一评估为低值。 Keeper节点也可以是预充电每个时钟周期的动态触发器输出。具有嵌入式逻辑的另一个触发器接收动态输出，应用更多的逻辑，并提供静态输出。

5. 发明授权

US06597223B2 Flip flop circuit 有权
公开(公告)号：US06597223B2
公开(公告)日：2003-07-22
申请号：US10208130
申请日：2002-07-30
申请人： Sriram R. Vangal , Dinesh Somasekhar
发明人： Sriram R. Vangal , Dinesh Somasekhar
IPC分类号： H03K3289
CPC分类号： H03K3/0372 , H03K3/356121
摘要： A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

6. 发明授权

US08769376B2 Memory cell supply voltage control based on error detection 有权
公开(公告)号：US08769376B2
公开(公告)日：2014-07-01
申请号：US13626435
申请日：2012-09-25
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

7. 发明授权

US08640005B2 Method and apparatus for using cache memory in a system that supports a low power state 有权
标题翻译：在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
公开(公告)号：US08640005B2
公开(公告)日：2014-01-28
申请号：US12785182
申请日：2010-05-21
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.
摘要翻译：高速缓冲存储器系统使用具有低存储和复杂度开销的多位错误校正码（ECC）。在一个实施例中，纠错逻辑可以包括：第一纠错逻辑，用于确定存储在高速缓存存储器的高速缓存行中的数据中的错误数;以及第二纠错逻辑，用于从第一纠错逻辑接收数据如果错误的数量被确定为大于1，并且响应于数据的接收执行错误校正。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。描述和要求保护其他实施例。

8. 发明申请

US20130275935A1 PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS 有权
标题翻译：从平面设计提供定时关闭FINFET设计
公开(公告)号：US20130275935A1
公开(公告)日：2013-10-17
申请号：US13446418
申请日：2012-04-13
申请人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
摘要翻译：公开了一种从平面设计提供定时关闭的FinFET设计的方法。实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

9. 发明授权

US08539303B2 Low overhead error correcting code protection for stored information 有权
标题翻译：存储信息的低开销错误纠正代码保护
公开(公告)号：US08539303B2
公开(公告)日：2013-09-17
申请号：US12973880
申请日：2010-12-20
申请人： Shih-Lien L. Lu , Dinesh Somasekhar
发明人： Shih-Lien L. Lu , Dinesh Somasekhar
IPC分类号： G06F11/00
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/05
摘要： Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values.
摘要翻译：公开了用于存储信息的低开销纠错码保护的发明的实施例。在一个实施例中，一种装置包括数据存储结构，第一检查值存储结构，第二检查值存储结构和检查值生成硬件。数据存储结构是存储多个第一数据值。第一检查值存储结构是存储多个第一检查值。第二检查值存储结构是存储多个第二检查值。检查值生成硬件是生成第一检查值和第二检查值。第一检查值为第一数据值提供第一级错误保护，并且第二检查值为多个第二数据值提供第二级别的错误保护。多个第一数据值中的每一个具有第一数据宽度，并且多个第二数据值中的每一个具有第二数据宽度，第二数据宽度大于第一数据宽度。第二数据值中的每一个是第一数据值和第一数据值中的至少另一数据值之一的级联。

10. 发明申请

US20110289380A1 METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE 有权
标题翻译：在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
公开(公告)号：US20110289380A1
公开(公告)日：2011-11-24
申请号：US12785182
申请日：2010-05-21
申请人： CHRISTOPHER B. WILKERSON , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： CHRISTOPHER B. WILKERSON , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064
摘要： A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.
摘要翻译：提供了一种使用具有低存储和复杂度开销的多位错误校正码（ECC）的高速缓冲存储器系统。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。

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