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1. 发明授权

US08433944B2 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle 失效
标题翻译：时钟分频器系统和方法具有增量调节步骤，同时控制时钟占空比的容限
公开(公告)号：US08433944B2
公开(公告)日：2013-04-30
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/00
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

2. 发明申请

US20110248764A1 Clock Divider System and Method 失效
标题翻译：时钟分频系统和方法
公开(公告)号：US20110248764A1
公开(公告)日：2011-10-13
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

3. 发明授权

US08760217B2 Semiconductor device having on-chip voltage regulator 有权
标题翻译：具有片上稳压器的半导体器件
公开(公告)号：US08760217B2
公开(公告)日：2014-06-24
申请号：US13034845
申请日：2011-02-25
申请人： Lew G. Chua-Eoan , Charlie Matar , Matthew L. Severson , Xiaohua Kong
发明人： Lew G. Chua-Eoan , Charlie Matar , Matthew L. Severson , Xiaohua Kong
IPC分类号： G11C5/14
CPC分类号： G06F1/26 , G06F1/3296 , H03K19/0016 , Y02D10/172
摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.
摘要翻译：公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。半导体器件包括位于接地总线和电源总线之间的电路。电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。监视器位于接地总线和电源总线之间。监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

4. 发明申请

US20120216089A1 Integrated Circuit Testing with Power Collapsed 有权
标题翻译：集成电路测试与电源崩溃
公开(公告)号：US20120216089A1
公开(公告)日：2012-08-23
申请号：US13032732
申请日：2011-02-23
申请人： Wei Chen , Yucong Tao , Matthew L. Severson , Jeffrey R. Gemar , Chang Yong Yang
发明人： Wei Chen , Yucong Tao , Matthew L. Severson , Jeffrey R. Gemar , Chang Yong Yang
IPC分类号： G06F11/00 , H03L5/00 , G01R31/40 , G06F19/00
CPC分类号： G01R31/3177 , G01R31/3008 , G01R31/318575
摘要： In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.
摘要翻译：在实例中，为集成电路提供了装置和方法。集成电路包括具有主电源域的第一集成电路部分和具有可折叠电源域的第二集成电路部分。集成电路还具有电平移位器，其具有耦合到第二电路部分的输入端和耦合到第一集成电路部分的输出端。电平移位器被配置为在可折叠电源域的电源被折叠时保持电平移位器输出的恒定。静态漏极电流测量电路可耦合以测试第二集成电路部分的至少一部分。边界扫描寄存器可以耦合在电平移位器输出和第一集成电路部分之间。集成电路还可以包括电源管理电路。

5. 发明授权

US08634790B2 Direct conversion receiver architecture with digital fine resolution variable gain amplification 有权
标题翻译：直接转换接收机架构，具有数字精细分辨率可变增益放大
公开(公告)号：US08634790B2
公开(公告)日：2014-01-21
申请号：US11131147
申请日：2005-05-16
申请人： Paul E. Peterzell , Christian Holenstein , Inyup Kang , Tao Li , Matthew L. Severson
发明人： Paul E. Peterzell , Christian Holenstein , Inyup Kang , Tao Li , Matthew L. Severson
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

6. 发明申请

US20110105070A1 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20110105070A1
公开(公告)日：2011-05-05
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H03L5/00 , H04B1/16
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

7. 发明授权

US08447007B2 Multi-clock real-time counter 有权
标题翻译：多时钟实时计数器
公开(公告)号：US08447007B2
公开(公告)日：2013-05-21
申请号：US13179852
申请日：2011-07-11
申请人： Matthew L. Severson
发明人： Matthew L. Severson
IPC分类号： H03K21/38 , G06F1/08
CPC分类号： H03K23/66 , G06F1/12 , G06F1/14
摘要： A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode.
摘要翻译：共享实时计数器被配置为当由快速时钟信号或慢时钟信号驱动时，基于快速时钟周期提供精确的计数器输出。组合逻辑电路在输入到计数器的快速时钟信号和计数器的慢时钟输入之间提供无毛刺切换。计数器始终处于开启状态，并且在快速时钟模式下，通过适当的合理数量的计数表示快速时钟的每个周期，并且通过适当的有理数量的快速时钟周期来增加其计数，以使每个周期的慢时钟信号，而在慢时钟模式。

8. 发明授权

US07076225B2 Variable gain selection in direct conversion receiver 失效
标题翻译：直接转换接收机中的可变增益选择
公开(公告)号：US07076225B2
公开(公告)日：2006-07-11
申请号：US10034734
申请日：2001-12-21
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

9. 发明授权

US08626099B2 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

10. 发明授权

US08615212B2 Direct conversion receiver architecture 有权
公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

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