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1. 发明申请

US20120198181A1 System and Method for Managing a Memory as a Circular Buffer 审中-公开
标题翻译：用于管理存储器作为循环缓冲器的系统和方法
公开(公告)号：US20120198181A1
公开(公告)日：2012-08-02
申请号：US13186431
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： G06F12/00
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

2. 发明授权

US08433944B2 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle 失效
标题翻译：时钟分频器系统和方法具有增量调节步骤，同时控制时钟占空比的容限
公开(公告)号：US08433944B2
公开(公告)日：2013-04-30
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/00
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

3. 发明申请

US20110248764A1 Clock Divider System and Method 失效
标题翻译：时钟分频系统和方法
公开(公告)号：US20110248764A1
公开(公告)日：2011-10-13
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

4. 发明授权

US08848731B2 System and method for facilitating data transfer using a shared non-deterministic bus 有权
标题翻译：使用共享非确定性总线促进数据传输的系统和方法
公开(公告)号：US08848731B2
公开(公告)日：2014-09-30
申请号：US13186391
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： G01S19/24 , G06F13/16 , G06F13/42 , G06F13/40 , G06F13/18 , G11C7/10
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

5. 发明申请

US20120198267A1 System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain 审中-公开
标题翻译：用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法
公开(公告)号：US20120198267A1
公开(公告)日：2012-08-02
申请号：US13186441
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： G06F1/04
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

6. 发明申请

US20120198117A1 System and Method for Improving Throughput of Data Transfers Using a Shared Non-Deterministic Bus 失效
标题翻译：使用共享非确定性总线提高数据传输吞吐量的系统和方法
公开(公告)号：US20120198117A1
公开(公告)日：2012-08-02
申请号：US13186416
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： G06F13/14
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

7. 发明授权

US08566491B2 System and method for improving throughput of data transfers using a shared non-deterministic bus 失效
标题翻译：使用共享非确定性总线提高数据传输吞吐量的系统和方法
公开(公告)号：US08566491B2
公开(公告)日：2013-10-22
申请号：US13186416
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： G06F13/18 , G06F13/364 , G06F13/16 , G11C7/10
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

8. 发明申请

US20120195350A1 System and Method for Facilitating Data Transfer Using a Shared Non-Deterministic Bus 有权
标题翻译：使用共享非确定性总线促进数据传输的系统和方法
公开(公告)号：US20120195350A1
公开(公告)日：2012-08-02
申请号：US13186391
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： H04L27/00 , H04B1/707
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

9. 发明授权

US06421757B1 Method and apparatus for controlling the programming and erasing of flash memory 有权
标题翻译：用于控制闪存编程和擦除的方法和装置
公开(公告)号：US06421757B1
公开(公告)日：2002-07-16
申请号：US09163776
申请日：1998-09-30
申请人： Peiqing Wang , Srinjoy Das
发明人： Peiqing Wang , Srinjoy Das
IPC分类号： G06F1200
CPC分类号： G11C16/10
摘要： A method and apparatus for automating and controlling the programming operations in a flash memory is provided to enable a microcontroller to accomplish various other controlling tasks while the programming operations are being conducted. A state machine is provided for controlling a plurality of sequences utilized in programming the flash memory, with various functional circuits provided to facilitate the programming and verification of flash memory cells. In a preferred embodiment, the reprogramming of the flash cells is limited to those flash cells verified as a programming failure, thus reducing the necessary programming of the flash memory cells which may impede the ability to program those flash cells. The control system may also be configured to provide for automating and controlling the erasing operations in a flash memory. The common interface circuitry may be employed to facilitates automation and control of both programming and erasing functions.
摘要翻译：提供了一种用于自动化和控制闪速存储器中的编程操作的方法和装置，以使微控制器能够在进行编程操作时完成各种其他控制任务。提供了一种状态机，用于控制在闪速存储器编程中使用的多个序列，其中提供了各种功能电路以便于闪速存储器单元的编程和验证。在优选实施例中，闪存单元的重新编程仅限于被验证为编程故障的那些闪存单元，从而减少闪速存储器单元的必要编程，这可能阻碍对闪存单元编程的能力。控制系统还可以被配置为提供自动化和控制闪速存储器中的擦除操作。可以采用公共接口电路来促进编程和擦除功能的自动化和控制。

10. 发明授权

US06233178B1 Method and apparatus for pre-conditioning flash memory devices 有权
标题翻译：用于预先安装闪存设备的方法和设备
公开(公告)号：US06233178B1
公开(公告)日：2001-05-15
申请号：US09418399
申请日：1999-10-14
申请人： Shyam Krishnamurthy , Srinjoy Das , Michael Le , Frank Van Gieson , Surya Bhattacharya , Umesh Sharma
发明人： Shyam Krishnamurthy , Srinjoy Das , Michael Le , Frank Van Gieson , Surya Bhattacharya , Umesh Sharma
IPC分类号： G11C700
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16
摘要： Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.
摘要翻译：公开了用于减轻闪速存储器件内的擦除引起的应力的预调节方法和装置。前提条件方法包括使闪速存储器单元进行短写入处理以至少部分地对单元进行放电。预条件处理一次应用于整个扇区，并且在擦除（充电）扇区内的单元之前立即执行。

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