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1. 发明授权

US06495887B1 Argon implantation after silicidation for improved floating-body effects 有权
标题翻译：硅化后的氩注入改善浮体效应
公开(公告)号：US06495887B1
公开(公告)日：2002-12-17
申请号：US09621290
申请日：2000-07-20
申请人： Srinath Krishnan , Witold P. Maszara , Matthew S. Buynoski
发明人： Srinath Krishnan , Witold P. Maszara , Matthew S. Buynoski
IPC分类号： H01L310392
CPC分类号： H01L29/66553 , H01L21/26506 , H01L21/76283 , H01L29/0653 , H01L29/458 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7841 , H01L29/78612 , H01L29/78621
摘要： A method of forming a MOSFET device is provided including the steps of forming N− lightly doped source and drain extension regions in the top silicon layer, forming spacers above the N− lightly doped source and drain extension regions and forming N+ source and N+ drain regions in the top silicon layer. A silicide film is then provided over the drain and source regions and the spacers are removed. An ion implantation step is then performed to form damaged sidewall regions in the source body and drain body junction.
摘要翻译：提供一种形成MOSFET器件的方法，包括以下步骤：在顶部硅层中形成N-轻掺杂的源极和漏极延伸区域，在N-轻掺杂的源极和漏极延伸区域上方形成间隔物并形成N +源极和N +漏极区域在顶层硅层。然后在漏极和源极区域上提供硅化物膜，并且去除间隔物。然后执行离子注入步骤以在源体和排水体结合处形成受损的侧壁区域。

2. 发明授权

US06872644B1 Semiconductor device with non-compounded contacts, and method of making 失效
标题翻译：具有非复合触点的半导体器件及其制造方法
公开(公告)号：US06872644B1
公开(公告)日：2005-03-29
申请号：US10126211
申请日：2002-04-19
申请人： Matthew S. Buynoski , Witold P. Maszara
发明人： Matthew S. Buynoski , Witold P. Maszara
IPC分类号： H01L21/22 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/38
CPC分类号： H01L29/66477 , H01L21/28044
摘要： A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.
摘要翻译：半导体器件包括源极和漏极接触区域，其包括半导体材料和至少一种金属的非复合组合。金属可以包括元素金属，例如金或铝，或者可以包括金属间化合物。接触区域可以通过在器件的源极和漏极上沉积有限量的至少一种金属而形成，并且退火该器件以诱导至少一种金属扩散到源极和漏极中。可以选择退火时间和温度来限制至少一种金属的扩散。

3. 发明授权

US06326247B1 Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer 有权
标题翻译：产生选择性薄的硅/氧化物以在相同的干燥剂上制造完全和部分耗尽的SOI的方法
公开(公告)号：US06326247B1
公开(公告)日：2001-12-04
申请号：US09606651
申请日：2000-06-28
申请人： Srinath Krishnan , Matthew S. Buynoski
发明人： Srinath Krishnan , Matthew S. Buynoski
IPC分类号： H01L2100
CPC分类号： H01L27/1203
摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. A semiconductive layer is provided having an oxide layer thereon. At least one trench is then etched into the oxide layer. The oxide layer is then filled with a substrate material layer and then ground and polished down to form a generally planar upper surface. The trench filled regions of the oxide layer form an oxide layer having regions of a first thickness and the remaining regions of the oxide layer are of a second thickness. The semiconductor wafer can then be flipped and partially depleted transistor devices formed over the regions of the first thickness and fully depleted transistor devices formed over regions of the second thickness.
摘要翻译：一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。提供其上具有氧化物层的半导体层。然后将至少一个沟槽蚀刻到氧化物层中。然后用基底材料层填充氧化物层，然后研磨并抛光，以形成大致平坦的上表面。氧化物层的沟槽填充区域形成具有第一厚度的区域的氧化物层，并且氧化物层的其余区域具有第二厚度。然后可以将半导体晶片翻转并在第二厚度的区域上形成的在第一厚度的区域上形成的部分耗尽的晶体管器件和完全耗尽的晶体管器件。

4. 发明授权

US06613643B1 Structure, and a method of realizing, for efficient heat removal on SOI 有权
标题翻译：结构和一种实现SOI上高效散热的方法
公开(公告)号：US06613643B1
公开(公告)日：2003-09-02
申请号：US10155044
申请日：2002-05-24
申请人： Srinath Krishnan , Matthew S. Buynoski
发明人： Srinath Krishnan , Matthew S. Buynoski
IPC分类号： H01L2176
CPC分类号： H01L21/76254
摘要： In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substrate by forming a pattern thereon; forming a first insulation layer over the first silicon substrate to provide a first structure and a second insulation layer over the second silicon substrate to provide a second structure; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the first or second silicon substrate thereby providing the silicon-on-insulator substrate.
摘要翻译：在一个实施例中，本发明涉及一种形成绝缘体上硅衬底的方法，包括提供第一硅衬底和第二硅衬底的步骤; 通过在其上形成图案来表面修饰第一硅衬底和第二硅衬底中的至少一个; 在所述第一硅衬底上形成第一绝缘层，以在所述第二硅衬底上方提供第一结构和第二绝缘层，以提供第二结构; 将第一结构和第二结构结合在一起，使得第一绝缘层与第二绝缘层相邻; 以及去除第一或第二硅衬底的一部分，从而提供绝缘体上硅衬底。

5. 发明授权

US07105421B1 Silicon on insulator field effect transistor with heterojunction gate 有权
公开(公告)号：US07105421B1
公开(公告)日：2006-09-12
申请号：US10835438
申请日：2004-04-29
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

6. 发明授权

US06815340B1 Method of forming an electroless nucleation layer on a via bottom 有权
标题翻译：在通孔底部形成无电解成核层的方法
公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译：制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物，以及使用合金在导电层的暴露部分上形成成核层。成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

7. 发明授权

US06784506B2 Silicide process using high K-dielectrics 失效
标题翻译：使用高K电介质的硅化物工艺
公开(公告)号：US06784506B2
公开(公告)日：2004-08-31
申请号：US09939744
申请日：2001-08-28
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2976
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.
摘要翻译：通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

8. 发明授权

US06759308B2 Silicon on insulator field effect transistor with heterojunction gate 有权
标题翻译：具有异质结栅的绝缘体上的场效应晶体管
公开(公告)号：US06759308B2
公开(公告)日：2004-07-06
申请号：US09902429
申请日：2001-07-10
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2130
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.
摘要翻译：在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。源极区和漏极区是具有第一杂质的重掺杂物。栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子。

9. 发明授权

US06667552B1 Low dielectric metal silicide lined interconnection system 失效
标题翻译：低介电金属硅化物衬里互连系统
公开(公告)号：US06667552B1
公开(公告)日：2003-12-23
申请号：US09252186
申请日：1999-02-18
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/32053 , H01L21/7682 , H01L21/76849 , H01L21/76852 , H01L23/5222 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/30105
摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and depositing a metal silicide to line the interconnection system. Embodiments include a semiconductor device comprising a dielectric sealing layer, e.g., silicon nitride, between the substrate and first patterned metal layer, tungsten silicide lining the interconnection system and dielectric protective layers, e.g., a silane derived oxide bottommost protective layer, on the uppermost metallization level.
摘要翻译：通过去除层间电介质和沉积金属硅化物以对互连系统进行排列，多级半导体器件形成具有减小的寄生电容，而不牺牲结构完整性或电迁移性能。实施例包括半导体器件，其包括在衬底和第一图案化金属层之间的电介质密封层，例如氮化硅，在互连系统衬里的硅化钨和介电保护层，例如最高金属化层上的硅烷衍生的氧化物最底层的保护层水平。

10. 发明授权

US06589866B1 Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法
公开(公告)号：US06589866B1
公开(公告)日：2003-07-08
申请号：US09691226
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2144
CPC分类号： H01L29/66545 , H01L21/28052 , H01L29/4933
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。然后在PVD非晶硅层上形成金属。另外的掺杂剂被注入到PVD非晶硅层中。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

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