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1. 发明申请

US20110040998A1 Oversampling-Based Scheme for Synchronous Interface Communication 失效
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US20110040998A1
公开(公告)日：2011-02-17
申请号：US12912521
申请日：2010-10-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F13/42 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

2. 发明授权

US07836324B2 Oversampling-based scheme for synchronous interface communication 有权
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US07836324B2
公开(公告)日：2010-11-16
申请号：US11740452
申请日：2007-04-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F13/42 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

3. 发明申请

US20080195884A1 Oversampling-Based Scheme for Synchronous Interface Communication 有权
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US20080195884A1
公开(公告)日：2008-08-14
申请号：US11740452
申请日：2007-04-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

4. 发明授权

US08307236B2 Oversampling-based scheme for synchronous interface communication 失效
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US08307236B2
公开(公告)日：2012-11-06
申请号：US12912521
申请日：2010-10-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F1/12 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

5. 发明授权

US08301941B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08301941B2
公开(公告)日：2012-10-30
申请号：US13305202
申请日：2011-11-28
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：设备可以包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可以由处理器编程成环回测试操作模式，并且在回送测试模式中，存储器控制器可以被配置为通过互连从处理器接收第一写入操作。存储器控制器可以被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。存储器控制器还可以被配置为在互连上将读数据作为读数据返回，用于从互连上的处理器接收到的第一读操作。

6. 发明申请

US20120072787A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20120072787A1
公开(公告)日：2012-03-22
申请号：US13305202
申请日：2011-11-28
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G06F11/26
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

7. 发明授权

US07836372B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US07836372B2
公开(公告)日：2010-11-16
申请号：US11760566
申请日：2007-06-08
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

8. 发明申请

US20080307286A1 Combined Single Error Correction/Device Kill Detection Code 有权
标题翻译：组合单错误纠正/设备杀毒检测码
公开(公告)号：US20080307286A1
公开(公告)日：2008-12-11
申请号：US11758322
申请日：2007-06-05
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，一种装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

9. 发明申请

US20080307276A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20080307276A1
公开(公告)日：2008-12-11
申请号：US11760566
申请日：2007-06-08
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G11C29/04 , G06F12/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

10. 发明申请

US20120017135A1 Combined Single Error Correction/Device Kill Detection Code 有权
标题翻译：组合单错误纠正/设备杀毒检测码
公开(公告)号：US20120017135A1
公开(公告)日：2012-01-19
申请号：US13246736
申请日：2011-09-27
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/09 , G06F11/08
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

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