专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5897666A Generation of unique address alias for memory disambiguation buffer to avoid false collisions 失效
标题翻译：生成内存消歧缓冲区的唯一地址别名，以避免错误的冲突
公开(公告)号：US5897666A
公开(公告)日：1999-04-27
申请号：US762791
申请日：1996-12-09
申请人： Soummya Mallick , Robert Greg McDonald
发明人： Soummya Mallick , Robert Greg McDonald
IPC分类号： G06F9/38 , G06F12/02
CPC分类号： G06F9/3834 , G06F9/3855
摘要： A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off. In the preferred embodiment, the memory addresses are 32-bit values, the array has 64 entries, and the encoder generates 6-bit values for the address aliases. The processor includes a memory disambiguation buffer for identifying load/store collisions, that uses the 6-bit address aliases.
摘要翻译：一种用于生成对应于存储器位置的地址别名的方法和装置，用于在存储器消除歧义期间避免虚假加载/存储冲突。别名生成器利用这样一个事实，即整个地址范围在任何一个时刻很可能不会在寄存器中被激活。活动的地址范围的子集可以用较少的比特数来表示，因此真正的依赖关系的计算大大减少。地址别名生成器包括用于接收存储器地址的阵列，具有连接到每个阵列条目并具有连接到别名编码器的输出的输入的比较器，以及用于在给定存储器地址之一中写入给定存储器地址的控制逻辑单元。如果存储器地址与对应于该输出的条目中的一个的内容相同，则给定门的输出被打开，并且如果所有门的输出被关闭，则控制装置被激活。在优选实施例中，存储器地址是32位值，该阵列具有64个条目，编码器为地址别名生成6位值。处理器包括用于识别加载/存储冲突的内存消歧缓冲器，其使用6位地址别名。

2. 发明授权

US5812812A Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue 失效
标题翻译：在采用无序指令问题的高性能数据处理系统中实现早期数据依赖解析机制的方法和系统
公开(公告)号：US5812812A
公开(公告)日：1998-09-22
申请号：US740911
申请日：1996-11-04
申请人： Muhammad Nural Afsar , Romesh Mangho Jessani , Soummya Mallick , Robert Greg McDonald , Mukesh Sharma
发明人： Muhammad Nural Afsar , Romesh Mangho Jessani , Soummya Mallick , Robert Greg McDonald , Mukesh Sharma
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384
摘要： A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.
摘要翻译：公开了一种利用无序指令问题的高性能数据处理系统实现早期数据依赖解析机制的方法和系统。根据本公开，提供了指令高速缓存和寄存器依赖性高速缓存。指令高速缓存具有多个高速缓存行，并且这些高速缓存行中的每一条都能够存储多个指令。寄存器依赖性高速缓存包含与指令高速缓存中相同数量的高速缓存行，并且寄存器相关高速缓存内的每个高速缓存线能够存储与每个高速缓存行中的指令相同数量的寄存器依赖单元在指令缓存中。在单个处理器周期中，从寄存器依赖性缓存中取出一组寄存器依赖单元。使用指令调度单元来识别在寄存器依赖单元组内没有转发数据依赖性的所有寄存器依赖单元。然后，使用所述指令高速缓存中的相应高速缓存行，将所识别的寄存器依赖单元中的每一个转换为其相应的指令。所有翻译的指令都是在下一个处理器周期内发出的。

3. 发明授权

US06240507B1 Mechanism for multiple register renaming and method therefor 失效
标题翻译：多重寄存器重命名机制及其方法
公开(公告)号：US06240507B1
公开(公告)日：2001-05-29
申请号：US09168794
申请日：1998-10-08
申请人： John Edward Derrick , Soummy A Mallick , Robert Greg McDonald
发明人： John Edward Derrick , Soummy A Mallick , Robert Greg McDonald
IPC分类号： G06F930
CPC分类号： G06F9/384 , G06F9/3013 , G06F9/3836 , G06F9/3857
摘要： An apparatus and method for renaming a plurality of storage register files implemented. A rename register in a unified rename buffer provides temporary storage for instruction operands resulting from the execution of the instruction to the operands being written to an architected register in one of storage register files. A rename map associates the rename register with the corresponding storage register, which may be in any of the storage register files. The rename registers may simultaneously store data values of different types. Rename map entries include a tag which operates to identify the register file containing the storage register.
摘要翻译：一种用于重命名实现的多个存储寄存器文件的装置和方法。统一重命名缓冲区中的重命名寄存器为指令操作数提供临时存储，这些操作数是由写入到存储寄存器文件之一中的架构寄存器的操作数的指令执行而产生的。重命名映射将重命名寄存器与相应的存储寄存器相关联，存储寄存器可以在任何存储寄存器文件中。重命名寄存器可以同时存储不同类型的数据值。重命名映射条目包括用于识别包含存储寄存器的寄存器文件的标签。

4. 发明授权

US06480931B1 Content addressable storage apparatus and register mapper architecture 有权
标题翻译：内容可寻址存储设备和寄存器映射器架构
公开(公告)号：US06480931B1
公开(公告)日：2002-11-12
申请号：US09434802
申请日：1999-11-05
申请人： Taqi Nasser Buti , Peter Juergen Klim , Hung Qui Le , Robert Greg McDonald
发明人： Taqi Nasser Buti , Peter Juergen Klim , Hung Qui Le , Robert Greg McDonald
IPC分类号： G06F1202
CPC分类号： G11C15/04 , G06F9/3836 , G06F9/3838 , G06F9/384 , G11C15/00
摘要： A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.
摘要翻译：提供非常规CAM（内容可寻址存储器）和寄存器映射器组织和电路实现，其允许同时执行大量CAM搜索。所有比较电路都放置在CAM外部，在实际比较发生的单独的匹配数组中。 CAM单元仅包含用于保存CAM存储的数据位的锁存器和用于更新CAM内容的多端口MUX。 CAM位被驱动到匹配数组以进行匹配生成。 CAM和搜索引擎的结构有助于将寄存器映射器实现为一组自定义阵列。每个阵列专用于执行特定功能。所有数组都对齐，数组的每一行都用于一个寄存器，以保持该寄存器的当前状态，阴影状态和控制。在示例性实施例中，八个定制阵列用于执行寄存器映射器的各种功能。

5. 发明授权

US06336183B1 System and method for executing store instructions 失效
标题翻译：执行存储指令的系统和方法
公开(公告)号：US06336183B1
公开(公告)日：2002-01-01
申请号：US09259140
申请日：1999-02-26
申请人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
发明人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F9312
CPC分类号： G06F9/3889 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.
摘要翻译：在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

6. 发明授权

US06484251B1 Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor 失效
标题翻译：基于无序处理器中的指令提交，基于设置/清除对中的指令特定修改信息更新状态寄存器
公开(公告)号：US06484251B1
公开(公告)日：2002-11-19
申请号：US09417824
申请日：1999-10-14
申请人： Robert Greg McDonald , Peichun Peter Liu , Christopher Hans Olson
发明人： Robert Greg McDonald , Peichun Peter Liu , Christopher Hans Olson
IPC分类号： G06F938
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.
摘要翻译：一种包括寄存器，执行单元，临时结果缓冲器和提交函数电路的处理器。寄存器包括至少一个寄存器位，并且可以包括一个或多个粘性位。执行单元适用于执行一组计算机指令。临时结果缓冲器被配置为从执行单元接收由指令提供的寄存器位修改信息。临时结果缓冲器适用于将修改信息存储在与寄存器的各个寄存器位对应的置位/清除位中。提交函数电路被配置为在提交指令时从临时结果缓冲器接收置位/清除的位对。提交函数电路适于响应于接收到置位/清除位对而产生更新的位。更新的位然后被提交到寄存器的相应寄存器位。

7. 发明授权

US06345356B1 Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs 失效
标题翻译：用于记分板的IOP的基于软件的调度失速机制的方法和装置
公开(公告)号：US06345356B1
公开(公告)日：2002-02-05
申请号：US09354498
申请日：1999-07-16
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
IPC分类号： G06F9312
CPC分类号： G06F9/3836 , G06F9/30018 , G06F9/30079 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation—Internal Operations (NOP—IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.
摘要翻译：发出虚拟指令，其次是几组无操作（NOP）。指令定序器单元（ISU）检测虚拟指令并停止流水线，直到记分板指示XER计数有效。从记分板专用寄存器（SPR）读取后，在写入和读取SPR IOP之间插入无操作内部操作（NOP-IOP），以允许在读取SPR IOP测试之前激活ISU记分板机制。使用读写读取序列：从记分板SPR中读取字符串计数字段，将该值写回相同的SPR，然后再次执行SPR的读取。预定数量的虚拟IOP跟随初始伪读取，以防止字串计数字段的值被读取太快。

8. 发明授权

US06256727B1 Method and system for fetching noncontiguous instructions in a single clock cycle 失效
标题翻译：在单个时钟周期内获取非连续指令的方法和系统
公开(公告)号：US06256727B1
公开(公告)日：2001-07-03
申请号：US09076593
申请日：1998-05-12
申请人： Robert Greg McDonald
发明人： Robert Greg McDonald
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3836
摘要： A system and method for fetching noncontiguous blocks of instructions in a data processing system is disclosed. The system comprises an instruction cache means for providing a first plurality of instructions and branch logic means for receiving the first plurality of instructions and for providing branch history information about the first plurality of instructions. The system further includes an auxiliary cache means for receiving a second plurality of instructions based upon the branch history information. The auxiliary cache means overlays at least one of the second plurality of instructions if there is a branch in the first plurality of instructions and the branch is to the second plurality of instructions.
摘要翻译：公开了一种用于在数据处理系统中取出非连续指令块的系统和方法。该系统包括用于提供第一多个指令的指令高速缓存装置和用于接收第一多个指令并用于提供关于第一多个指令的分支历史信息的分支逻辑装置。该系统还包括辅助高速缓存装置，用于基于分支历史信息接收第二多个指令。如果在第一多个指令中存在分支并且分支是第二多个指令，则辅助高速缓存装置覆盖第二多个指令中的至少一个指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式