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1. 发明授权

US07788617B2 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis 失效
标题翻译：在定时分析期间建模和采用CMOS栅极的方法和输出负载相关的引脚电容
公开(公告)号：US07788617B2
公开(公告)日：2010-08-31
申请号：US12043455
申请日：2008-03-06
申请人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
发明人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.
摘要翻译：一种精确的方法来计算电容与电容相关的引脚上的电容。该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。产生来自压摆和输出负载的针电容表的RC / RLC网络。所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。

2. 发明申请

US20090228850A1 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis 失效
标题翻译：在定时分析期间建模和采用CMOS栅极的方法和输出负载相关的引脚电容
公开(公告)号：US20090228850A1
公开(公告)日：2009-09-10
申请号：US12043455
申请日：2008-03-06
申请人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
发明人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
IPC分类号： G06F9/45
CPC分类号： G06F17/5031
摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.
摘要翻译：一种精确的方法来计算电容与电容相关的引脚上的电容。该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。产生来自压摆和输出负载的针电容表的RC / RLC网络。所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。

3. 发明授权

US08103997B2 Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits 有权
标题翻译：在VLSI电路定时抽取过程中采用与摆率相关的引脚电容捕获互连寄生效应的方法
公开(公告)号：US08103997B2
公开(公告)日：2012-01-24
申请号：US12426492
申请日：2009-04-20
申请人： Debjit Sinha , Soroush Abbaspour , Adil Bhanji , Jeffrey M. Ritzinger
发明人： Debjit Sinha , Soroush Abbaspour , Adil Bhanji , Jeffrey M. Ritzinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
摘要翻译：用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。采用互连模型订单减少来加速流程。在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

4. 发明申请

US20100269083A1 Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of VLSI Circuits 有权
标题翻译：在定时抽取VLSI电路的过程中采用压摆相关引脚电容捕获互连寄生的方法
公开(公告)号：US20100269083A1
公开(公告)日：2010-10-21
申请号：US12426492
申请日：2009-04-20
申请人： Debjit Sinha , Soroush Abbaspour , Adil Bhanji , Jeffrey M. Ritzinger
发明人： Debjit Sinha , Soroush Abbaspour , Adil Bhanji , Jeffrey M. Ritzinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
摘要翻译：用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。采用互连模型订单减少来加速流程。在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

5. 发明申请

US20090077515A1 Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise 失效
标题翻译：串扰导致噪声的约束进攻器集合选择方法
公开(公告)号：US20090077515A1
公开(公告)日：2009-03-19
申请号：US11855323
申请日：2007-09-14
申请人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
发明人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
摘要翻译：执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响。给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

6. 发明申请

US20110016442A1 Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics 有权
标题翻译：考虑抽象单元的互连寄存器进行静态时序分析的方法
公开(公告)号：US20110016442A1
公开(公告)日：2011-01-20
申请号：US12503924
申请日：2009-07-16
申请人： Soroush Abbaspour , Debjit Sinha
发明人： Soroush Abbaspour , Debjit Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.
摘要翻译：支持多层次级别的抽象模型被输入到分层IC芯片设计的广义静态时序分析中，以分析和优化包含多个宏抽象的芯片集成的电路的设计。为内部抽象互连段合成的电气网络每宏执行一次，并应用于IC芯片设计中的宏抽象模型的多个实例。合成电网是阻性电容或电阻感应电容网络或其组合。然后使用合成的电气网络来匹配网络的脉冲响应传递函数和抽象互连段的时序模型。该网络与连接到宏主要输出的外部互连段的电气寄生线缝合。然后在网络拼接之前对外部互连的电寄生效应进行各种模型顺序减少。在最终网络上执行静态时序分析。

7. 发明授权

US08122411B2 Method of performing static timing analysis considering abstracted cell's interconnect parasitics 有权
标题翻译：考虑抽象单元的互连寄生效应执行静态时序分析的方法
公开(公告)号：US08122411B2
公开(公告)日：2012-02-21
申请号：US12503924
申请日：2009-07-16
申请人： Soroush Abbaspour , Debjit Sinha
发明人： Soroush Abbaspour , Debjit Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.
摘要翻译：支持多层次级别的抽象模型被输入到分层IC芯片设计的广义静态时序分析中，以分析和优化包含多个宏抽象的芯片集成的电路的设计。为内部抽象互连段合成的电气网络每宏执行一次，并应用于IC芯片设计中的宏抽象模型的多个实例。合成电网是阻性电容或电阻感应电容网络或其组合。然后使用合成的电气网络来匹配网络的脉冲响应传递函数和抽象互连段的时序模型。该网络与连接到宏主要输出的外部互连段的电气寄生线缝合。然后在网络拼接之前对外部互连的电寄生效应进行各种模型顺序减少。在最终网络上执行静态时序分析。

8. 发明授权

US07685549B2 Method of constrained aggressor set selection for crosstalk induced noise 失效
标题翻译：串扰引起噪声的约束入侵者集合选择方法
公开(公告)号：US07685549B2
公开(公告)日：2010-03-23
申请号：US11855323
申请日：2007-09-14
申请人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
发明人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
摘要翻译：执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响。给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

9. 发明申请

US20120124542A1 Method and System for Optimizing a Device With Current Source Models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

10. 发明申请

US20120123725A1 PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US20120123725A1
公开(公告)日：2012-05-17
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅里叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

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