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1. 发明授权

US06198705B1 Error-tolerant target-sector search using previous N sector ID for high-speed CD 有权
标题翻译：使用先前的N扇区ID进行高速CD的容错目标扇区搜索
公开(公告)号：US06198705B1
公开(公告)日：2001-03-06
申请号：US09153949
申请日：1998-09-16
申请人： Phuc Thanh Tran , Son Hong Ho , Hung Cao Nguyen
发明人： Phuc Thanh Tran , Son Hong Ho , Hung Cao Nguyen
IPC分类号： G11B1722
CPC分类号： G11B15/68 , G11B17/22
摘要： An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the sector-search hardware. The disk-controller firmware writes a virtual target register the previous sector's header's minutes, seconds, frame (MSF), which is one less that the desired sector's MSF, or MSF-1. A physical target that precedes the virtual target is searched for. The physical target precedes the desired sector by N sectors, so that the physical target is MSF-N. When the physical target matches a header read from the disk, a good sector found flag is set. The physical target is then incremented for each new sector and compared to the virtual target. Once the physical target matches the virtual target, the following sector is buffered to the host. The raw header from the disk is stored and error corrections are made using the error correction byte following the sector's data. The corrected raw header is compared to the virtual target to determine if the correct sector was captured. The virtual target is also incremented so that all following sectors that are transferred to the host can also have their headers checked.
摘要翻译：光盘控制器以高速读取CD-ROM盘，这通常会产生错误。识别扇区的标头中的错误被扇区搜索硬件所容忍。磁盘控制器固件将虚拟目标寄存器写入前一个扇区的标题的分钟，秒，帧（MSF），其小于所需扇区的MSF或MSF-1。搜索虚拟目标之前的物理目标。物理目标在N个扇区之前在期望扇区之前，使得物理目标是MSF-N。当物理目标与从磁盘读取的头匹配时，设置好的扇区发现标志。然后，为每个新扇区增加物理目标，并与虚拟目标进行比较。一旦物理目标与虚拟目标匹配，则下列扇区被缓存到主机。存储磁盘中的原始标题，并使用扇区数据后的纠错字节进行错误更正。将校正的原始报头与虚拟目标进行比较，以确定是否捕获了正确的扇区。虚拟目标也会递增，以便传输到主机的所有以下扇区也可以检查其头。

2. 发明授权

US06249896B1 Error-tolerant sync detection for DVD optical disks using programmable sequence of sync marks 有权
标题翻译：使用可编程序同步标记的DVD光盘进行容错同步检测
公开(公告)号：US06249896B1
公开(公告)日：2001-06-19
申请号：US09251724
申请日：1999-02-17
申请人： Son Hong Ho , Hung Cao Nguyen , Phuc Thanh Tran
发明人： Son Hong Ho , Hung Cao Nguyen , Phuc Thanh Tran
IPC分类号： G11B2700
CPC分类号： G11B20/1813 , G11B27/3027 , G11B2220/2562
摘要： Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched. Once initial sync is made, the bit timing is adjusted when too many pseudo-sync clocks are inserted for sync marks missed due to jitter. An early and a late window around the expected sync point are used to enable re-sync to a detected fixed sync pattern.
摘要翻译：最初检测到数字通用光盘（DVD）光盘上的同步（同步）标记，稍后用于调整抖动发生后的位时序。每个DVD物理扇区以预定义的顺序包含许多同步标记。每个同步标记具有对于扇区中的同步标记而变化的同步码字段，以及对于所有同步标记是恒定的固定同步模式。通过检测在第一同步标记之前的同步标记的同步码的先前序列，在初始化时检测第一同步标记。该序列是可编程的，以便搜索到一个到七个同步标记。由于可以在每个同步码和固定同步码型中允许可编程位数的错误，所以仍然会发生具有位错误的同步标记的检测。其中一个同步代码可能会被错过，并且仍然进行检测，从而允许在较长序列的同步码匹配时容许同步标记中的错误。一旦进行初始同步，当针对由于抖动丢失的同步标记插入太多伪同步时钟时，调整位定时。围绕预期同步点的早期和晚期窗口用于使得能够重新同步到检测到的固定同步模式。

3. 发明授权

US6115837A Dual-column syndrome generation for DVD error correction using an embedded DRAM 失效
标题翻译：使用嵌入式DRAM进行DVD纠错的双列校正子生成
公开(公告)号：US6115837A
公开(公告)日：2000-09-05
申请号：US124334
申请日：1998-07-29
申请人： Hung Cao Nguyen , Son Hong Ho
发明人： Hung Cao Nguyen , Son Hong Ho
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2220/2562 , G11C2029/0411
摘要： A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded memory buffer. The block has rows and columns. Row syndromes are generated on-the-fly as the data is written from the DVD disk to the memory buffer. Row syndrome generation thus requires no memory access cycles. Once errors in the rows identified by the row syndromes are corrected, column syndromes are generated. A multi-byte fetch supplies a multi-column syndrome generator with bytes in the row for two or more columns. The fetched bytes for the two or more columns are accumulated into intermediate syndromes. Fetched bytes are accumulated for other rows until all of the column's bytes in all rows have been fetched and accumulated. The final accumulated syndromes are output to an error corrector that detects, locates, and corrects any errors in the columns. The same error corrector can be used for row and column syndromes, even though a three-block-deep pipeline is used. Only one memory access cycle is required during column-syndrome generation for each row, even though two or more column syndromes are simultaneously generated. Pipelined registers for the intermediate syndrome bytes in the column-syndrome generator allow syndrome-calculation circuits to be shared for all column syndromes.
摘要翻译：数字通用盘（DVD）播放控制器集成电路（IC）将数据写入嵌入式存储器缓冲器中的块。该块具有行和列。随着数据从DVD磁盘写入到内存缓冲区，行综合征是随机生成的。因此，行综合征生成不需要存储器访问周期。一旦校正了由行综合征识别的行中的错误，就会生成列综合征。多字节提取为多列校正子生成器提供了两列或更多列的行中的字节。两个或更多列的获取字节被累积到中间综合征中。直到所有行中的所有列的字节都已被获取和累积为止，才会为其他行累积获取的字节。最终累积的综合征被输出到错误校正器，以检测，定位和校正列中的任何错误。即使使用三块深的管道，相同的误差校正器也可用于行和列综合征。即使两个或多个列综合征同时生成，在每一行的列综合征生成期间只需要一个存储器访问周期。列综合征发生器中的中间综合征字节的流水线寄存器允许对所有列综合征共享校正子计算电路。

4. 发明授权

US06279135B1 On-the-fly row-syndrome generation for DVD controller ECC 有权
标题翻译：用于DVD控制器ECC的即时行综合征生成
公开(公告)号：US06279135B1
公开(公告)日：2001-08-21
申请号：US09197323
申请日：1998-11-19
申请人： Hung Cao Nguyen , Son Hong Ho
发明人： Hung Cao Nguyen , Son Hong Ho
IPC分类号： G11C2900
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2220/2562 , G11C2029/0411
摘要： A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded memory buffer while row syndromes are being generated in parallel. The block has rows and columns. Row syndromes are generated on-the-fly as the data is written from the DVD disk to the memory buffer. Row syndrome generation thus requires no memory access cycles. Column syndrome generation is delayed until row correction is completed. Once errors in the rows identified by the row syndromes are corrected, column syndromes are generated. The bytes received from the DVD disk for the current row are accumulated into intermediate row syndromes. Received bytes are accumulated for the row until all of the row's bytes have been received and accumulated. The final accumulated row syndromes are written to the embedded memory buffer for later row error-correction. The row syndromes are later sent from the embedded memory buffer to an error corrector that detects, locates, and corrects any errors in the rows. A separate SRAM buffer for error correction is eliminated even though on-the-fly performance is achieved.
摘要翻译：数字多功能盘（DVD）回放控制器集成电路（IC）将数据写入嵌入式存储器缓冲器中的块，同时并行生成行综合征。该块具有行和列。随着数据从DVD磁盘写入到内存缓冲区，行综合征是随机生成的。因此，行综合征生成不需要存储器访问周期。列校正生成被延迟，直到行校正完成。一旦校正了由行综合征识别的行中的错误，就会生成列综合征。从当前行的DVD盘接收到的字节被累积到中间行综合征中。接收到的字节被累积，直到所有行的字节都被接收和累积。最后累积的行综合征被写入到嵌入式存储器缓冲器中用于稍后的行纠错。行综合征随后从嵌入式存储器缓冲区发送到错误校正器，该错误校正器检测，定位和校正行中的任何错误。即使实现了即时性能，也可以消除用于纠错的单独的SRAM缓冲器。

5. 发明授权

US6167551A DVD controller with embedded DRAM for ECC-block buffering 失效
标题翻译：具有嵌入式DRAM的DVD控制器，用于ECC块缓冲
公开(公告)号：US6167551A
公开(公告)日：2000-12-26
申请号：US124332
申请日：1998-07-29
申请人： Hung Cao Nguyen , Son Hong Ho
发明人： Hung Cao Nguyen , Son Hong Ho
IPC分类号： H03M13/00
CPC分类号： G11B20/00
摘要： An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes. The full width is used for writing data from the optical disk to the ECC data block buffer, and for reading data from the host-buffer area to the host. Narrower access widths are used by the error correction and de-scrambler blocks.
摘要翻译：嵌入式DRAM集成在数字通用盘（DVD）播放控制器集成电路内。来自DVD光盘的数据被写入嵌入式DRAM中的数据块。通过读取数据块来执行错误校正，以在校正中产生校正子和数据块中的写入错误。一旦数据块被纠正，它将被复制或移动到嵌入式存储器，主机 - 缓冲区域的不同区域。当移动数据块时，执行去加扰来解密数据。重新排序的数据被剥离诸如ECC字节的开销，并写入嵌入式DRAM的主机缓冲区。随着数据移动，生成校验和，并将校验和与存储的校验和进行比较，以确保所有错误得到纠正。然后将主机缓冲区中的数据块传送到主机。嵌入式DRAM具有非常宽的16字节的数据访问宽度。全宽用于将数据从光盘写入ECC数据块缓冲区，并将数据从主机缓冲区读取到主机。较窄的访问宽度由纠错和解扰器块使用。

6. 发明申请

US20120182640A1 DUAL CHANNEL HDD SYSTEMS AND METHODS 有权
标题翻译：双通道HDD系统和方法
公开(公告)号：US20120182640A1
公开(公告)日：2012-07-19
申请号：US13352744
申请日：2012-01-18
申请人： Son Hong Ho
发明人： Son Hong Ho
IPC分类号： G11B5/09 , G11B27/36
CPC分类号： G11B5/09 , G11B5/59666 , G11B19/044 , G11B20/10527 , G11B20/1883 , G11B2020/1062 , G11B2220/2516
摘要： A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a disk of the hard disk assembly. The second channel module is configured to receive a second data from or transfer the second data to a second amplifier module of the hard disk assembly when reading or writing to a second surface of the disk while the first channel module receives the first data from or transfers the first data to the first amplifier module.
摘要翻译：硬盘驱动器系统包括第一通道模块和第二通道模块。第一通道模块被配置为当从硬盘组件的盘的第一表面读取或写入硬盘组件的第一表面时从第一数据接收第一数据或将其传送到硬盘组件的第一放大器模块。第二通道模块被配置为当第一通道模块从第一通道模块或第二通道模块接收到第一数据时，在读取或写入盘的第二表面时从第二数据接收第二数据或将其传送到硬盘组件的第二放大器模块将第一个数据传送到第一个放大器模块。

7. 发明授权

US07840878B1 Systems and methods for data-path protection 有权
标题翻译：数据路径保护的系统和方法
公开(公告)号：US07840878B1
公开(公告)日：2010-11-23
申请号：US11711286
申请日：2007-02-27
申请人： Heng Tang , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
发明人： Heng Tang , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/1803 , H03M13/09 , H03M13/253 , H03M13/2915
摘要： A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.
摘要翻译：系统包括主机先进先出（FIFO）模块，第一编码器模块，控制模块，盘FIFO模块和第二编码器模块。主机FIFO模块接收具有数据的块并选择性地接收主机逻辑块地址（HLBA）。第一编码器模块基于数据和HLBA生成第一校验和，并生成第一编码块。控制模块将HLBA附加到第一编码块并生成附加块。磁盘FIFO模块从主机FIFO模块接收该块。第二编码器模块基于HLBA和由盘FIFO模块接收的块中的数据选择性地产生第二校验和。第二编码器模块基于第一和第二校验和将由盘FIFO模块接收的块与由主机FIFO模块接收的块进行比较。

8. 发明授权

US6105107A ATAPI state machine controlled by a microcontroller for interfacing a DVD controller with an ATA host bus 失效
标题翻译：由微控制器控制的ATAPI状态机用于将DVD控制器与ATA主机总线进行接口
公开(公告)号：US6105107A
公开(公告)日：2000-08-15
申请号：US126118
申请日：1998-07-30
申请人： Son Hong Ho , Kevin Hung Tonthat
发明人： Son Hong Ho , Kevin Hung Tonthat
IPC分类号： G06F3/06 , G06F11/10 , G06F12/00
CPC分类号： G06F3/0607 , G06F11/10 , G06F3/0632 , G06F3/0677
摘要： A digital-versatile disk (DVD) controller interfaces to an AT bus using ATAPI commands delivered in command packets. A microcontroller executes firmware routines to control the servo that positions the read head, and reads data sectors from the DVD disk. The microcontroller also performs error correction on the DVD data in a disk buffer. A host state machine is used to interface to the AT bus. State transitions in the host state machine are enabled or blocked by the microcontroller by setting auto-transition bits in a state-control register. The microcontroller can set auto bits to allow the host state machine to automatically receive multi-byte command packets, or to transfer data or send status to the host without microcontroller intervention. The microcontroller also has the option of performing any of these steps manually, such as for more complex ATAPI commands. Overlapping ATAPI commands are allowed when the AT bus is released. The host state machine can be programmed to wait for a service command from the host after the bus is released, and then automatically transfer data or status. Transfer errors send interrupts to the microcontroller so it can execute recovery routines.
摘要翻译：数字通用磁盘（DVD）控制器使用ATAPI命令与命令包中的ATAPI命令相连接。微控制器执行固件程序来控制定位读取头的伺服器，并从DVD盘读取数据扇区。微控制器还对磁盘缓冲区中的DVD数据执行纠错。主机状态机用于与AT总线的接口。通过在状态控制寄存器中设置自动转换位，微控制器启用或阻止主机状态机中的状态转换。微控制器可以设置自动位以允许主机状态机自动接收多字节命令数据包，或者在无需微控制器干预的情况下传输数据或发送状态到主机。微控制器还可以手动执行这些步骤，例如更复杂的ATAPI命令。当AT总线被释放时，允许重叠的ATAPI命令。总线释放后，主机状态机可编程为等待来自主机的服务命令，然后自动传输数据或状态。传输错误向微控制器发送中断，因此可以执行恢复例程。

9. 发明授权

US08484537B1 Systems and methods for data-path protection 有权
标题翻译：数据路径保护的系统和方法
公开(公告)号：US08484537B1
公开(公告)日：2013-07-09
申请号：US12950779
申请日：2010-11-19
申请人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
发明人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/1803 , H03M13/09 , H03M13/253 , H03M13/2915
摘要： A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.
摘要翻译：一种包括第一缓冲器模块，第一编码器模块，控制模块和第二缓冲器模块的系统。第一缓冲器模块从主机接收（i）第一块和（ii）第一块的第一逻辑块地址（LBA），其中第一块包括第一数据。第一编码器模块基于（i）第一数据和（ii）第一LBA产生第一校验和。控制模块生成第二块，其中第二块包括（i）第一数据，（ii）第一LBA，和（iii）第一校验和。第二缓冲器模块从第一缓冲器模块接收第三块，其中第三块包括第二LBA。第二缓冲器模块根据第三块中的第二LBA是否不同于第二块中的第一LBA来确定第三块是否不同于第一块。

10. 发明授权

US08373422B2 Integrated systems testing 有权
标题翻译：集成系统测试
公开(公告)号：US08373422B2
公开(公告)日：2013-02-12
申请号：US13006958
申请日：2011-01-14
申请人： Saeed Azimi , Son Hong Ho
发明人： Saeed Azimi , Son Hong Ho
IPC分类号： G01R31/04 , G01R31/3187
CPC分类号： G11B20/182 , G01R31/3004 , G01R31/31716 , G01R31/31717 , G11B5/455
摘要： A system including an interface and a plurality of solder joint testing modules. The interface is configured to receive test configuration data to configure each of a plurality of integrated system test (IST) modules. Each of the plurality of solder joint testing modules is configured to, based on the test configuration data, i) apply a pulse having a predetermined amplitude and width to a solder joint associated with a respective one of the plurality of IST modules, ii) monitor a resultant waveform that is generated in response to the pulse, and iii) determine an integrity of the solder joint in response to the resultant waveform. Each of the plurality of solder joint testing modules and the respective ones of the plurality of IST modules are located on a same system on chip (SOC).
摘要翻译：一种包括接口和多个焊点测试模块的系统。该接口被配置为接收测试配置数据以配置多个集成系统测试（IST）模块中的每一个。多个焊点测试模块中的每一个被配置为：基于测试配置数据，i）将具有预定幅度和宽度的脉冲施加到与多个IST模块中的相应一个模块相关联的焊点，ii）监视响应于脉冲而产生的合成波形，以及iii）响应于所得到的波形来确定焊点的完整性。多个焊点测试模块中的每一个和多个IST模块中的相应的IST模块位于相同的片上系统（SOC）上。

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