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1. 发明授权

US06809623B2 High Q on-chip inductor 失效
标题翻译：高Q片上电感
公开(公告)号：US06809623B2
公开(公告)日：2004-10-26
申请号：US10087614
申请日：2002-03-01
申请人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
发明人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
IPC分类号： H01F500
CPC分类号： H01L27/08 , H01F17/0006 , H01F17/0013 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49082 , Y10T29/4914
摘要： A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.
摘要翻译：高Q片上电感器包括初级绕组和辅助绕组，其被耦合以接收初级绕组的输入的成比例地相反的表示。此外，辅助绕组具有大于初级绕组的导纳的导纳，从而导致导电不对称。因此，在片内电感器产生大的Q因子的2端口系统（例如，初级绕组的第1和第2个节点）中获得推/拉机构。

2. 发明授权

US07236080B2 On-chip high Q inductor 有权
标题翻译：片上高Q电感
公开(公告)号：US07236080B2
公开(公告)日：2007-06-26
申请号：US10944305
申请日：2004-09-17
申请人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
发明人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
IPC分类号： H01F5/00 , H03H5/00
CPC分类号： H01L27/08 , H01F17/0006 , H01F17/0013 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49082 , Y10T29/4914
摘要： A high-Q on-chip inductor includes a primary winding and an auxiliary winding. The primary winding includes a first node and a second node. The auxiliary winding is operably coupled to increase a quality factor of the primary winding.
摘要翻译：高Q片上电感器包括初级绕组和辅助绕组。初级绕组包括第一节点和第二节点。辅助绕组可操作地耦合以增加初级绕组的品质因数。

3. 发明申请

US20050030145A1 On-chip high Q inductor 有权
标题翻译：片上高Q电感
公开(公告)号：US20050030145A1
公开(公告)日：2005-02-10
申请号：US10944305
申请日：2004-09-17
申请人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
发明人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
IPC分类号： H01F17/00 , H01L27/08 , H01F5/00
CPC分类号： H01L27/08 , H01F17/0006 , H01F17/0013 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49082 , Y10T29/4914
摘要： A high-Q on-chip inductor includes a primary winding and an auxiliary winding. The primary winding includes a first node and a second node. The auxiliary winding is operably coupled to increase a quality factor of the primary winding.
摘要翻译：高Q片上电感器包括初级绕组和辅助绕组。初级绕组包括第一节点和第二节点。辅助绕组可操作地耦合以增加初级绕组的品质因数。

4. 发明授权

US07032292B2 Method of manufacturing high Q on-chip inductor 有权
标题翻译：制造高Q片上电感的方法
公开(公告)号：US07032292B2
公开(公告)日：2006-04-25
申请号：US10395568
申请日：2003-03-24
申请人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
发明人： Sissy Kyriazidou , Harry Contopanagos , Reza Rofougaran
IPC分类号： H01F7/06 , H01F5/00 , H01C10/06
CPC分类号： H01L27/08 , H01F17/0006 , H01F17/0013 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49082 , Y10T29/4914
摘要： A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.
摘要翻译：高Q片上电感器包括初级绕组和辅助绕组，其被耦合以接收初级绕组的输入的成比例地相反的表示。此外，辅助绕组具有大于初级绕组的导纳的导纳，从而导致导电不对称。因此，在产生大Q因子的2端口系统（例如，初级绕组的1 和2 节点）中获得推/拉机构用于片上电感。

5. 发明授权

US06979608B2 Method of manufacturing an on-chip inductor having improved quality factor 有权
标题翻译：制造具有改善品质因素的片上电感器的方法
公开(公告)号：US06979608B2
公开(公告)日：2005-12-27
申请号：US10673874
申请日：2003-09-29
申请人： Harry Contopanagos , Christos Komninakis , Sissy Kyriazidou
发明人： Harry Contopanagos , Christos Komninakis , Sissy Kyriazidou
IPC分类号： H04B1/40 , H01L21/8238 , H01L21/20 , H01L21/8234 , H01L21/8244
CPC分类号： H04B1/406
摘要： An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer having a major surface parallel to a major surface of the dielectric layer, (2) field oxide layer having a major surface parallel to a major surface of the dielectric layer, (3) P-well and field oxide layer, or (4) a poly-silicon layer having a major surface parallel to a major surface of the dielectric layer.
摘要翻译：可以通过产生至少一个介电层来制造片上电感器，在至少一个电介质层上产生至少一个导电绕组，并产生：（1）P阱层，其主表面平行于电介质层，（2）具有平行于电介质层的主表面的主表面的场氧化物层，（3）P阱和场氧化物层，或（4）主表面平行于电介质层的主表面。

6. 发明授权

US06937128B2 On-chip inductor having a square geometry and high Q factor and method of manufacture thereof 有权
标题翻译：具有正方形几何形状和高Q因子的片上电感器及其制造方法
公开(公告)号：US06937128B2
公开(公告)日：2005-08-30
申请号：US10074158
申请日：2002-02-12
申请人： Harry Contopanagos , Sissy Kyriazidou
发明人： Harry Contopanagos , Sissy Kyriazidou
IPC分类号： H01L27/08 , H01F5/00
CPC分类号： H01L27/08 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073
摘要： An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.
摘要翻译：片上电感器和/或片上变压器包括至少一个电介质层和至少一个电介质层上的至少一个导电绕组。导电绕组具有基本上正方形的几何形状，并且至少具有几何形状的外部角，以减小导电绕组在特定工作频率下的阻抗。由于片上电感的品质因数与工作频率下的电感器的有效串联阻抗成反比，通过降低有效串联阻抗，提高了品质因数。

7. 发明申请

US20050250467A1 Unconditionally stable filter 有权
标题翻译：无条件稳定过滤
公开(公告)号：US20050250467A1
公开(公告)日：2005-11-10
申请号：US11182580
申请日：2005-07-15
申请人： Harry Contopanagos , Chryssoula Kyriazidou , Jacob Rael , Ahmadreza Rofougaran
发明人： Harry Contopanagos , Chryssoula Kyriazidou , Jacob Rael , Ahmadreza Rofougaran
IPC分类号： H03H7/01 , H03H11/32 , H03H11/52 , H04B1/18 , H04B17/00 , H04B1/16
CPC分类号： H03H7/03 , H03H7/0115 , H03H7/175 , H03H7/1758 , H03H7/1766 , H03H7/1775 , H03H7/425 , H03H11/52 , H03H2007/013 , H04B1/18
摘要： An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.
摘要翻译：无条件稳定的片上滤波器包括滤波部分和至少一个负电阻模块。滤波部分可操作地耦合以对信号进行滤波并且包括可实现的集成电路无源部件。至少一个负电阻模块可操作地耦合以补偿滤波部分的集成电路损耗。可实现的集成电路无源元件具有鲁棒性，与寄生值相比具有最小的集成电路空间，并为包括CMOS技术在内的各种集成电路制造工艺提供可实现的值。

8. 发明授权

US07109947B2 Methods of generating a magnetic interface 有权
标题翻译：产生磁性界面的方法
公开(公告)号：US07109947B2
公开(公告)日：2006-09-19
申请号：US11091548
申请日：2005-03-29
申请人： Nicolaos G. Alexopoulos , Harry Contopanagos , Chryssoula Kyriazidou
发明人： Nicolaos G. Alexopoulos , Harry Contopanagos , Chryssoula Kyriazidou
IPC分类号： H01Q1/36
CPC分类号： H01P1/2005 , H01P3/08 , H01Q9/0407 , H01Q9/27 , H01Q15/002 , H01Q15/0066 , H01Q15/008 , H01Q21/062
摘要： A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface. For example, the magnetic interface can be used to increase the inductance of a printed inductor circuit, and to increase the gain and match of a microstrip patch antenna. Furthermore, the magnetic interface reduces the traverse electric (TE) and transverse magnetic (TM) surface waves in the plane of the magnetic interface, which reduces unwanted coupling between transmission lines.
摘要翻译：磁接口发生器以中心频率f 0 0生成磁接口。磁接口发生器是沉积在衬底表面上的无源螺旋阵列。磁性界面在衬底表面上方距离Z的平面中产生。产生磁性界面的距离Z由螺旋阵列的单元尺寸确定，其中单元尺寸基于螺旋臂长度和螺旋之间的间隔S. 磁性界面的中心频率由螺旋阵列中的螺旋线的平均轨道长度D 决定。在实施例中，螺旋阵列是多层衬底中的一个子层。选择螺旋阵列的间隔S将磁性界面投影到多层基板中的另一层，以便提高磁性界面平面中的电路的性能。例如，磁性接口可用于增加印刷电感器电路的电感，并增加微带贴片天线的增益和匹配。此外，磁接口减小了磁接口平面中的横向电（TE）和横向磁（TM）表面波，从而减少了传输线之间的不必要的耦合。

9. 发明授权

US06944435B2 Unconditionally stable on-chip filter and applications thereof 失效
标题翻译：无条件稳定的片上滤波器及其应用
公开(公告)号：US06944435B2
公开(公告)日：2005-09-13
申请号：US10160915
申请日：2002-06-03
申请人： Harry Contopanagos , Chryssoula Kyriazidou , Jacob Rael , Ahmadreza Rofougaran
发明人： Harry Contopanagos , Chryssoula Kyriazidou , Jacob Rael , Ahmadreza Rofougaran
IPC分类号： H03H7/01 , H03H11/32 , H03H11/52 , H04B1/18 , H04B1/10
CPC分类号： H03H7/03 , H03H7/0115 , H03H7/175 , H03H7/1758 , H03H7/1766 , H03H7/1775 , H03H7/425 , H03H11/52 , H03H2007/013 , H04B1/18
摘要： An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.
摘要翻译：无条件稳定的片上滤波器包括滤波部分和至少一个负电阻模块。滤波部分可操作地耦合以对信号进行滤波并且包括可实现的集成电路无源部件。至少一个负电阻模块可操作地耦合以补偿滤波部分的集成电路损耗。可实现的集成电路无源元件具有鲁棒性，与寄生值相比，具有最小的集成电路空间，并为包括CMOS技术在内的各种集成电路制造工艺提供可实现的值。

10. 发明申请

US20050168314A1 Methods of generating a magnetic interface 有权
标题翻译：产生磁性界面的方法
公开(公告)号：US20050168314A1
公开(公告)日：2005-08-04
申请号：US11091548
申请日：2005-03-29
申请人： Nicolaos Alexopoulos , Harry Contopanagos , Chryssoula Kyriazidou
发明人： Nicolaos Alexopoulos , Harry Contopanagos , Chryssoula Kyriazidou
IPC分类号： H01P3/08 , H01Q9/04 , H01Q9/27 , H01Q15/00 , H01Q21/06 , H01F5/00
CPC分类号： H01P1/2005 , H01P3/08 , H01Q9/0407 , H01Q9/27 , H01Q15/002 , H01Q15/0066 , H01Q15/008 , H01Q21/062
摘要： A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface. For example, the magnetic interface can be used to increase the inductance of a printed inductor circuit, and to increase the gain and match of a microstrip patch antenna. Furthermore, the magnetic interface reduces the traverse electric (TE) and transverse magnetic (TM) surface waves in the plane of the magnetic interface, which reduces unwanted coupling between transmission lines.
摘要翻译：磁接口发生器以中心频率f 0 0生成磁接口。磁接口发生器是沉积在衬底表面上的无源螺旋阵列。磁性界面在衬底表面上方距离Z的平面中产生。产生磁性界面的距离Z由螺旋阵列的单元尺寸确定，其中单元尺寸基于螺旋臂长度和螺旋之间的间隔S. 磁性界面的中心频率由螺旋阵列中的螺旋线的平均轨道长度D 决定。在实施例中，螺旋阵列是多层衬底中的一个子层。选择螺旋阵列的间隔S将磁性界面投影到多层基板中的另一层，以便提高磁性界面平面中的电路的性能。例如，磁性接口可用于增加印刷电感器电路的电感，并增加微带贴片天线的增益和匹配。此外，磁接口减小了磁接口平面中的横向电（TE）和横向磁（TM）表面波，从而减少了传输线之间的不必要的耦合。

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