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1. 发明授权

US08487431B2 Semiconductor integrated circuit having a multi-chip structure 有权
标题翻译：具有多芯片结构的半导体集成电路
公开(公告)号：US08487431B2
公开(公告)日：2013-07-16
申请号：US12833436
申请日：2010-07-09
申请人： Sin-Hyun Jin , Jong-Chern Lee
发明人： Sin-Hyun Jin , Jong-Chern Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
摘要翻译：具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

2. 发明申请

US20110291266A1 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MULTI-CHIP STRUCTURE 有权
标题翻译：具有多芯片结构的半导体集成电路
公开(公告)号：US20110291266A1
公开(公告)日：2011-12-01
申请号：US12833436
申请日：2010-07-09
申请人： Sin-Hyun Jin , Jong-Chern Lee
发明人： Sin-Hyun Jin , Jong-Chern Lee
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
摘要翻译：具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

3. 发明授权

US08760181B2 Semiconductor system and device for identifying stacked chips and method thereof 有权
标题翻译：用于识别堆叠芯片的半导体系统和装置及其方法
公开(公告)号：US08760181B2
公开(公告)日：2014-06-24
申请号：US12914424
申请日：2010-10-28
申请人： Sang-Jin Byeon , Jong-Chern Lee
发明人： Sang-Jin Byeon , Jong-Chern Lee
IPC分类号： G01R31/36 , G11C5/02
CPC分类号： G11C11/4072 , G06F2213/0038 , G11C7/10 , G11C8/12 , G11C11/4076 , G11C16/20
摘要： A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.
摘要翻译：用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据比较结果。

4. 发明授权

US08482331B2 Open loop type delay locked loop and method for operating the same 失效
标题翻译：开环型延时锁定环及其操作方法
公开(公告)号：US08482331B2
公开(公告)日：2013-07-09
申请号：US12832549
申请日：2010-07-08
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K2005/00104
摘要： An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
摘要翻译：开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟响应代码值。

5. 发明授权

US08451037B2 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08451037B2
公开(公告)日：2013-05-28
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

6. 发明授权

US08314476B2 Semiconductor chip and semiconductor wafer 有权
标题翻译：半导体芯片和半导体晶圆
公开(公告)号：US08314476B2
公开(公告)日：2012-11-20
申请号：US12833672
申请日：2010-07-09
申请人： Jun-Gi Choi , Jong-Chern Lee
发明人： Jun-Gi Choi , Jong-Chern Lee
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.
摘要翻译：半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

7. 发明申请

US20120154002A1 DELAY LOCKED LOOP 失效
标题翻译：延迟锁定环
公开(公告)号：US20120154002A1
公开(公告)日：2012-06-21
申请号：US13400967
申请日：2012-02-21
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03L7/08
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

8. 发明授权

US08143925B2 Delay locked loop 失效
标题翻译：延迟锁定环路
公开(公告)号：US08143925B2
公开(公告)日：2012-03-27
申请号：US12753442
申请日：2010-04-02
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

9. 发明授权

US08946869B2 Integrated circuit for detecting defects of through chip via 有权
标题翻译：用于检测芯片通孔缺陷的集成电路
公开(公告)号：US08946869B2
公开(公告)日：2015-02-03
申请号：US13041003
申请日：2011-03-04
申请人： Dae-Suk Kim , Jong-Chern Lee , Chul Kim
发明人： Dae-Suk Kim , Jong-Chern Lee , Chul Kim
IPC分类号： H01L29/00 , H01L29/80 , H01L23/48 , H01L21/66 , G01R31/28 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2853 , G01R31/2884 , H01L23/481 , H01L24/05 , H01L2225/06544 , H01L2225/06596 , H01L2924/12032 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.
摘要翻译：在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流，在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

10. 发明授权

US08436651B2 Command control circuit for semiconductor integrated device 有权
标题翻译：半导体集成装置的指令控制电路
公开(公告)号：US08436651B2
公开(公告)日：2013-05-07
申请号：US12624144
申请日：2009-11-23
申请人： Hyun-Su Yoon , Jong-Chern Lee
发明人： Hyun-Su Yoon , Jong-Chern Lee
IPC分类号： G06F7/38
CPC分类号： H04L7/02 , H04L7/0045
摘要： A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.
摘要翻译：半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

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