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    • 3. 发明申请
    • DELAY LOCKED LOOP
    • 延迟锁定环
    • US20120154002A1
    • 2012-06-21
    • US13400967
    • 2012-02-21
    • Seung-Joon AHNJong-Chern Lee
    • Seung-Joon AHNJong-Chern Lee
    • H03L7/08
    • H03L7/0816H03L7/0814
    • A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
    • 延迟锁定环包括复制延迟振荡器单元,除法单元,脉冲发生单元,代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号,并响应于延迟锁定检测信号,以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。
    • 4. 发明授权
    • Delay locked loop
    • 延迟锁定环路
    • US08143925B2
    • 2012-03-27
    • US12753442
    • 2010-04-02
    • Seung-Joon AhnJong-Chern Lee
    • Seung-Joon AhnJong-Chern Lee
    • H03L7/06
    • H03L7/0816H03L7/0814
    • A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
    • 延迟锁定环包括复制延迟振荡器单元,除法单元,脉冲发生单元,代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号,并响应于延迟锁定检测信号,以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。
    • 5. 发明授权
    • Delay locked loop and method for driving the same
    • 延迟锁定环和驱动方法
    • US08446197B2
    • 2013-05-21
    • US12755949
    • 2010-04-07
    • Seung-Joon AhnJong-Chern Lee
    • Seung-Joon AhnJong-Chern Lee
    • H03L7/00
    • H03L7/0814H03L7/07
    • A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.
    • 延迟锁定环包括延迟脉冲产生单元,编码单元和延迟线。 延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。 编码单元被配置为对延迟脉冲进行编码并输出代码值。 延迟线被配置为通过代码值来延迟输入时钟,并产生延迟的锁定时钟。 延迟脉冲在与第一周期(对应于输入时钟的整数倍)和第二周期(在某个复制延迟周期)之间的差值的第三周期内具有逻辑高电平状态。
    • 7. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08233339B2
    • 2012-07-31
    • US12875803
    • 2010-09-03
    • Hyun-Su YoonJong-Chern LeeSeung-Joon Ahn
    • Hyun-Su YoonJong-Chern LeeSeung-Joon Ahn
    • G11C7/00
    • G11C7/22G11C7/222G11C2207/2272
    • A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
    • 半导体存储器件包括开环型延迟锁定环(DLL),其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号 等待时间控制单元,被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令,并输出移位的命令;以及附加延迟线,被配置为根据延迟代码值来延迟移位的命令 对应于第二延迟量,并且输出控制哪个操作定时的命令。
    • 10. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20120008433A1
    • 2012-01-12
    • US12875803
    • 2010-09-03
    • Hyun-Su YOONJong-Chern LeeSeung-Joon Ahn
    • Hyun-Su YOONJong-Chern LeeSeung-Joon Ahn
    • G11C7/00
    • G11C7/22G11C7/222G11C2207/2272
    • A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
    • 半导体存储器件包括开环型延迟锁定环(DLL),其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号 等待时间控制单元,被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令,并输出移位的命令;以及附加延迟线,被配置为根据延迟代码值来延迟移位的命令 对应于第二延迟量,并且输出控制哪个操作定时的命令。