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1. 发明申请

US20130290635A1 PROVISION OF ACCESS CONTROL DATA WITHIN A DATA PROCESSING SYSTEM 有权
标题翻译：在数据处理系统中提供访问控制数据
公开(公告)号：US20130290635A1
公开(公告)日：2013-10-31
申请号：US13881113
申请日：2011-09-27
申请人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
发明人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
IPC分类号： G06F12/14 , G06F12/08
CPC分类号： G06F12/1416 , G06F12/0802 , G06F12/1441 , G06F12/145 , G06F12/1458 , Y02D10/13
摘要： A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory address range addresses within that region.
摘要翻译：数据处理系统（2）包括存储器保护电路（10），存储用于控制对主存储器（16）内的存储器地址上的数据的访问的访问控制数据。在一个实施例中，当访问控制数据由存储器保护电路（10）指示为可高速缓存时，访问控制高速缓存（14）可以存储访问控制数据。在另一个实施例中，访问控制数据被存储在具有确定的地址范围数据的访问控制高速缓存内，以由存储器保护电路进行访问控制数据的确定。如果访问控制缓存（14）正在存储用于存储器访问请求的访问控制数据，则使用存储在访问控制高速缓存（14）内的访问控制数据来代替从存储器保护电路（10）检索的访问控制数据，。在第一实施例中，如果与包围该区域内的所有存储器地址范围地址的最高阶区域的多个层次顺序的存储器地址中的存储器地址的区域相关联，则可以确定访问控制数据可高速缓存。

2. 发明授权

US09639484B2 Provision of access control data within a data processing system 有权
公开(公告)号：US09639484B2
公开(公告)日：2017-05-02
申请号：US13881113
申请日：2011-09-27
申请人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
发明人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
IPC分类号： G06F12/00 , G06F12/14 , G06F12/0802
CPC分类号： G06F12/1416 , G06F12/0802 , G06F12/1441 , G06F12/145 , G06F12/1458 , Y02D10/13
摘要： A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

3. 发明授权

US09753724B2 Conditional selection of data elements 有权
公开(公告)号：US09753724B2
公开(公告)日：2017-09-05
申请号：US13200348
申请日：2011-09-23
申请人： Simon John Craske , Richard Roy Grisenthwaite , Nigel John Stephens
发明人： Simon John Craske , Richard Roy Grisenthwaite , Nigel John Stephens
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30072 , G06F9/30094 , G06F9/3842
摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

4. 发明授权

US08756377B2 Area and power efficient data coherency maintenance 有权
标题翻译：区域和功率有效的数据一致性维护
公开(公告)号：US08756377B2
公开(公告)日：2014-06-17
申请号：US12656538
申请日：2010-02-02
申请人： Simon John Craske , Antony John Penton , Loic Pierron , Andrew Christopher Rose
发明人： Simon John Craske , Antony John Penton , Loic Pierron , Andrew Christopher Rose
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0804 , G06F2212/1024 , Y02D10/13
摘要： An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device.
摘要翻译：公开了一种用于存储正在处理的数据的装置。该装置包括：与处理器相关联的用于存储在存储器中用于由处理器使用的数据项的本地副本的高速缓存，用于监控与高速缓存相关联的监视电路，用于监视由另一设备发起的存储器的写事务请求，进一步的设备被配置为不将数据存储在高速缓存中。监视电路响应于检测到写入事务请求来写入其本地副本存储在高速缓存中的数据项，以阻止从存储器发送到指示写入已完成的另一设备的写入确认信号，并使其无效存储的本地副本在缓存中并完成无效，以将写入确认信号发送到另一个设备。

5. 发明授权

US08499017B2 Apparatus and method for performing fused multiply add floating point operation 有权
标题翻译：用于执行融合乘法添加浮点运算的装置和方法
公开(公告)号：US08499017B2
公开(公告)日：2013-07-30
申请号：US12461478
申请日：2009-08-12
申请人： Antony John Penton , Simon John Craske , Ian Michael Caulfield
发明人： Antony John Penton , Simon John Craske , Ian Michael Caulfield
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/5443 , G06F7/483
摘要： A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C having a high order portion 160 and a low order portion 170. The apparatus has adding circuitry 130 configured to: (i) add an operand A to one of the high order portion 160 and the low order portion 170 to generate an intermediate sum value; and (ii) add the intermediate sum value to a remaining one of the high order portion 160 and the low order portion 170 to generate a result A+B*C.
摘要翻译：数据处理装置被配置为执行融合乘法运算。装置100具有被配置为将操作数B和C相乘以产生具有高阶部分160和低阶部分170的乘积B * C的乘法电路110.该装置具有加法电路130，其被配置为：（i）将操作数A 到高阶部分160和低阶部分170中的一个以产生中间和值; 和（ii）将中间和值添加到高阶部分160和低阶部分170中的剩余部分，以产生结果A + B * C。

6. 发明申请

US20130097408A1 CONDITIONAL COMPARE INSTRUCTION 有权
标题翻译：条件比较指导
公开(公告)号：US20130097408A1
公开(公告)日：2013-04-18
申请号：US13637757
申请日：2011-04-12
申请人： David James Seal , Simon John Craske
发明人： David James Seal , Simon John Craske
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/30072 , G06F9/30167
摘要： An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.
摘要翻译：指令解码器（14）响应于条件比较指令以产生用于控制处理电路（4）执行条件比较操作的控制信号。条件比较操作包括：（i）如果处理电路（4）的当前条件状态通过测试条件，则对第一操作数和第二操作数执行比较操作，并将当前条件状态设置为结果条件状态在比较操作期间产生; 和（ii）如果当前条件状态未通过测试条件，则将当前状态设置为由条件比较指令指定的故障状态。条件比较指令可以用于表示比较操作的链接序列，其中每个单独的比较操作可以测试一对操作数之间的不同种类的关系。

7. 发明授权

US07925866B2 Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权
标题翻译：用于处理由处理电路执行的指令的数据处理装置和方法
公开(公告)号：US07925866B2
公开(公告)日：2011-04-12
申请号：US12314095
申请日：2008-12-03
申请人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske , Max Zardini
发明人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske , Max Zardini
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30149 , G06F9/3816 , G06F9/382 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要翻译：提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

8. 发明申请

US20100325358A1 Data storage protocols to determine items stored and items overwritten in linked data stores 有权
标题翻译：用于确定存储的项目的数据存储协议和链接数据存储中覆盖的项目
公开(公告)号：US20100325358A1
公开(公告)日：2010-12-23
申请号：US12457812
申请日：2009-06-22
申请人： Paul Gilbert Meyer , David James Williamson , Simon John Craske
发明人： Paul Gilbert Meyer , David James Williamson , Simon John Craske
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/1054 , G06F2212/682
摘要： A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle. The storage apparatus comprises: two stores each for storing a subset of the plurality of items, the first access request being routed to a first store and said second access request to a second store; miss detecting circuitry for detecting a miss where a requested item is not stored in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in a respective one of the two stores in dependence upon an access history of the respective store, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.
摘要翻译：公开了一种用于存储多个物品的存储装置和方法。存储装置被配置为接收在相同时钟周期中访问各个项目的第一访问请求和第二访问请求。存储装置包括：两个存储器，每个存储器用于存储多个项目的子集，第一访问请求被路由到第一存储器，并且所述第二访问请求传送到第二存储器; 用于检测未请求的未检测电路，其中所请求的项目不存储在所访问的存储器中; 项目检索电路，用于检索其访问从另一商店中产生未命中的项目; 更新电路，用于根据相应存储器的访问历史来选择要在两个存储器中的相应一个存储器中重写的项目，所述更新电路响应于所述未检测电路检测到对所述第一存储器的访问中的遗漏并且处于至少一个进一步的条件是通过覆盖所选择的项目来更新从另外的商店检索的商品的两个商店。

9. 发明申请

US20100241777A1 Power efficient interrupt detection 有权
标题翻译：高效的中断检测
公开(公告)号：US20100241777A1
公开(公告)日：2010-09-23
申请号：US12382751
申请日：2009-03-23
申请人： Mittu Xavier Kocherry , Simon John Craske , Chiloda Ashan Senerath Pathirane , David Michael Gilday
发明人： Mittu Xavier Kocherry , Simon John Craske , Chiloda Ashan Senerath Pathirane , David Michael Gilday
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry.
摘要翻译：公开了用于检测并向处理器输出中断请求的中断请求检测电路。所述中断请求检测电路包括：用于接收中断信号的中断信号输入; 用于从处理器接收指示处理器当前正在处理中断的信号的输入; 检测电路，用于检测中断请求并向数据处理装置输出中断请求信号; 用于禁用所述检测电路的至少一部分的禁用逻辑; 其中响应于检测到所述处理器正在处理中断; 检测电路被配置为检测由断言指示中断请求的中断信号引起的中断信号的变化，并且响应于检测到中断信号断言而将中断请求信号输出到输出电路; 并且响应于检测到处理器当前未处理中断; 所述禁用逻辑被配置为禁用所述检测电路的至少一部分; 并且具有至少部分禁用的检测电路被配置为将中断信号作为中断请求信号输出到输出电路。

10. 发明申请

US20100199072A1 Register file 有权
标题翻译：注册文件
公开(公告)号：US20100199072A1
公开(公告)日：2010-08-05
申请号：US12320710
申请日：2009-02-02
申请人： Simon John Craske
发明人： Simon John Craske
IPC分类号： G06F9/30
CPC分类号： G06F9/30141
摘要： A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request received at said at least one write port to update one of said plurality of register entries identified by an address specified by said write request with a data value specified by said write request. The register file also comprises further circuitry responsive to a received control signal to set at least a portion of a predetermined register entry to a predetermined value. In this way, certain register file updating instructions can be executed in parallel with other instructions without the need for additional full write-ports as would be required for typical dual-issue, thereby reducing area and routing complexity and cost compared with the use of an additional write-port due to the lower gate count required by the proposed further circuitry.
摘要翻译：提供了包括用于存储用于执行数据处理指令的数据值的多个寄存器条目的寄存器文件，并且包括至少一个写入端口和至少一个读取端口，以及响应于在所述数据处理指令处接收到的写入请求的电路至少一个写入端口，用于通过由所述写请求指定的数据值来更新由所述写请求指定的地址所标识的所述多个寄存器条目之一。寄存器文件还包括响应于接收的控制信号的另外的电路，以将预定寄存器条目的至少一部分设置为预定值。以这种方式，可以与其他指令并行地执行某些寄存器文件更新指令，而不需要像典型的双重问题所需的额外的完整写入端口，从而与使用由于所提出的另外的电路所需的较低的栅极数，由于额外的写入端口。

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