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1. 发明申请

US20120110396A1 Error handling mechanism for a tag memory within coherency control circuitry 有权
标题翻译：一致性控制电路内的标签存储器的错误处理机制
公开(公告)号：US20120110396A1
公开(公告)日：2012-05-03
申请号：US12926142
申请日：2010-10-27
申请人： Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
发明人： Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
IPC分类号： G06F12/08 , G06F11/16
CPC分类号： G06F11/1064 , G06F12/0806 , Y02D10/13
摘要： A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.
摘要翻译：数据处理系统2设置有多个处理器核心4,6,8,10，每个处理器核心包含数据高速缓冲存储器12,14,16,18。监视控制单元20管理存储在数据高速缓冲存储器12,14,16,18内的数据值之间的一致性。侦听控制单元20包含TAG存储器22.如果在TAG存储器22的条目内检测到错误，则命中操作被强制到对应的存储位置，一个或多个数据高速缓冲存储器12 ，14,16,18。

2. 发明申请

US20130151819A1 RECOVERING FROM EXCEPTIONS AND TIMING ERRORS 有权
标题翻译：从异常和时序错误中恢复
公开(公告)号：US20130151819A1
公开(公告)日：2013-06-13
申请号：US13313053
申请日：2011-12-07
申请人： Frederic Claude Marie PIRY , Luca SCALABRINO , Guillaume SCHON , Melanie Emanuelle Lucie TEYSSIER
发明人： Frederic Claude Marie PIRY , Luca SCALABRINO , Guillaume SCHON , Melanie Emanuelle Lucie TEYSSIER
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/38 , G06F9/384 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/0772 , G06F11/0793 , G06F11/1407
摘要： A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
摘要翻译：具有处理流水线的数据处理装置，流水线包括异常控制电路和错误检测电路。异常存储单元被配置为维护与发出到处理流水线的指令相对应的条目的年龄排序列表以供执行。该单元被配置为与每个条目相关联地存储指示指令是异常指令的异常指示以及它是否已经产生异常以及指示指令是否已经产生错误的错误指示符。所述装置被配置为在所述指令的处理已经到达已知所述指令是否将产生错误以及所述指令是否将产生异常的阶段时向所述异常存储单元指示指令被解析; 并且异常控制电路被配置为从异常存储单元中的列表中顺序地退出最旧的解析条目。

3. 发明授权

US09189432B2 Apparatus and method for predicting target storage unit 有权
标题翻译：用于预测目标存储单元的装置和方法
公开(公告)号：US09189432B2
公开(公告)日：2015-11-17
申请号：US12926394
申请日：2010-11-15
申请人： Melanie Emanuelle Lucie Teyssier , Florent Begon , Jocelyn Francois Orion Jaubert , Nicolas Jean Phillippe Huot
发明人： Melanie Emanuelle Lucie Teyssier , Florent Begon , Jocelyn Francois Orion Jaubert , Nicolas Jean Phillippe Huot
IPC分类号： G06F15/00 , G06F7/38 , G06F9/44 , G06F9/00 , G06F13/16 , G06F9/34 , G06F9/38
CPC分类号： G06F13/16 , G06F9/30043 , G06F9/34 , G06F9/383 , G06F9/3832
摘要： A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.
摘要翻译：数据处理装置包括处理电路和多个存储单元。当处理电路执行数据访问指令时，存储控制器基于数据访问指令的目标存储地址来识别哪个存储单元包括由目标存储地址识别的目标存储位置。提供预测电路以预测预测包括目标存储位置的预测存储单元，使得可以在存储控制器识别目标存储单元之前从预测存储单元检索数据值。预测电路根据由处理电路执行的数据访问指令的类型进行预测。

4. 发明申请

US20130290635A1 PROVISION OF ACCESS CONTROL DATA WITHIN A DATA PROCESSING SYSTEM 有权
标题翻译：在数据处理系统中提供访问控制数据
公开(公告)号：US20130290635A1
公开(公告)日：2013-10-31
申请号：US13881113
申请日：2011-09-27
申请人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
发明人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
IPC分类号： G06F12/14 , G06F12/08
CPC分类号： G06F12/1416 , G06F12/0802 , G06F12/1441 , G06F12/145 , G06F12/1458 , Y02D10/13
摘要： A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory address range addresses within that region.
摘要翻译：数据处理系统（2）包括存储器保护电路（10），存储用于控制对主存储器（16）内的存储器地址上的数据的访问的访问控制数据。在一个实施例中，当访问控制数据由存储器保护电路（10）指示为可高速缓存时，访问控制高速缓存（14）可以存储访问控制数据。在另一个实施例中，访问控制数据被存储在具有确定的地址范围数据的访问控制高速缓存内，以由存储器保护电路进行访问控制数据的确定。如果访问控制缓存（14）正在存储用于存储器访问请求的访问控制数据，则使用存储在访问控制高速缓存（14）内的访问控制数据来代替从存储器保护电路（10）检索的访问控制数据，。在第一实施例中，如果与包围该区域内的所有存储器地址范围地址的最高阶区域的多个层次顺序的存储器地址中的存储器地址的区域相关联，则可以确定访问控制数据可高速缓存。

5. 发明授权

US09052909B2 Recovering from exceptions and timing errors 有权
标题翻译：从异常和定时错误中恢复
公开(公告)号：US09052909B2
公开(公告)日：2015-06-09
申请号：US13313053
申请日：2011-12-07
申请人： Frederic Claude Marie Piry , Luca Scalabrino , Guillaume Schon , Melanie Emanuelle Lucie Teyssier
发明人： Frederic Claude Marie Piry , Luca Scalabrino , Guillaume Schon , Melanie Emanuelle Lucie Teyssier
IPC分类号： G06F9/00 , G06F15/00 , G06F9/44 , G06F9/38
CPC分类号： G06F9/38 , G06F9/384 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/0772 , G06F11/0793 , G06F11/1407
摘要： A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
摘要翻译：具有处理流水线的数据处理装置，流水线包括异常控制电路和错误检测电路。异常存储单元被配置为维护与发出到处理流水线的指令相对应的条目的年龄排序列表以供执行。该单元被配置为与每个条目相关联地存储指示指令是异常指令的异常指示以及它是否已经产生异常以及指示指令是否已经产生错误的错误指示符。所述装置被配置为在所述指令的处理已经到达已知所述指令是否将产生错误以及所述指令是否将产生异常的阶段时向所述异常存储单元指示指令被解析; 并且异常控制电路被配置为从异常存储单元中的列表中顺序地退出最旧的解析条目。

6. 发明授权

US09639484B2 Provision of access control data within a data processing system 有权
公开(公告)号：US09639484B2
公开(公告)日：2017-05-02
申请号：US13881113
申请日：2011-09-27
申请人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
发明人： Simon John Craske , Melanie Emanuelle Lucie Teyssier , Nicolas Jean Phillippe Huot , Gilles Eric Grandou
IPC分类号： G06F12/00 , G06F12/14 , G06F12/0802
CPC分类号： G06F12/1416 , G06F12/0802 , G06F12/1441 , G06F12/145 , G06F12/1458 , Y02D10/13
摘要： A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

7. 发明授权

US08458532B2 Error handling mechanism for a tag memory within coherency control circuitry 有权
标题翻译：一致性控制电路内的标签存储器的错误处理机制
公开(公告)号：US08458532B2
公开(公告)日：2013-06-04
申请号：US12926142
申请日：2010-10-27
申请人： Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
发明人： Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/0806 , Y02D10/13
摘要： A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.
摘要翻译：数据处理系统2设置有多个处理器核心4,6,8,10，每个处理器核心包含数据高速缓冲存储器12,14,16,18。监视控制单元20管理存储在数据高速缓冲存储器12,14,16,18内的数据值之间的一致性。侦听控制单元20包含TAG存储器22.如果在TAG存储器22的条目内检测到错误，则命中操作被强制到对应的存储位置，一个或多个数据高速缓冲存储器12 ，14,16,18。

8. 发明申请

US20120124300A1 Apparatus and method for predicting target storage unit 有权
标题翻译：用于预测目标存储单元的装置和方法
公开(公告)号：US20120124300A1
公开(公告)日：2012-05-17
申请号：US12926394
申请日：2010-11-15
申请人： Melanie Emanuelle Lucie Teyssier , Florent Begon , Jocelyn Francois Orion Jaubert , Nicolas Jean Phillippe Huot
发明人： Melanie Emanuelle Lucie Teyssier , Florent Begon , Jocelyn Francois Orion Jaubert , Nicolas Jean Phillippe Huot
IPC分类号： G06F12/00
CPC分类号： G06F13/16 , G06F9/30043 , G06F9/34 , G06F9/383 , G06F9/3832
摘要： A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.
摘要翻译：数据处理装置包括处理电路和多个存储单元。当处理电路执行数据访问指令时，存储控制器基于数据访问指令的目标存储地址来识别哪个存储单元包括由目标存储地址识别的目标存储位置。提供预测电路以预测预测包括目标存储位置的预测存储单元，使得可以在存储控制器识别目标存储单元之前从预测存储单元检索数据值。预测电路根据由处理电路执行的数据访问指令的类型进行预测。

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