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    • 7. 发明授权
    • Object detection
    • 对象检测
    • US07522772B2
    • 2009-04-21
    • US11007110
    • 2004-12-08
    • Robert Mark Stefan PorterJonathan LivingSimon Dominic Haynes
    • Robert Mark Stefan PorterJonathan LivingSimon Dominic Haynes
    • G06K9/68
    • G06K9/00228
    • Image object detection apparatus in which test regions of a test image are compared with an image property model, a mask defining a subset of pixel positions within a test region, comprises means for comparing pixel properties in the test image defined by the test regions with the image property model to detect a property difference between the image property model and a test region; so that pixel property differences within the mask and pixel property differences outside the mask are combined with opposite respective polarities to form a difference value in respect of that test region, an object being detected in the test image at a test region corresponding to a lowest difference value between the image property model and pixels defined by the test region.
    • 将测试图像的测试区域与图像属性模型进行比较的图像对象检测设备,定义测试区域内的像素位置子集的掩模,包括用于将由测试区域定义的测试图像中的像素属性与 图像属性模型,用于检测图像属性模型和测试区域之间的属性差异; 使得掩模之外的掩模和像素特性差异中的像素特性差异与相对的相应极性组合以形成关于该测试区域的差值,在与最低差对应的测试区域的测试图像中检测到的对象 图像属性模型与由测试区域定义的像素之间的值。
    • 8. 发明授权
    • Object detection
    • 对象检测
    • US07489803B2
    • 2009-02-10
    • US11007097
    • 2004-12-08
    • Simon Dominic HaynesJonathan Living
    • Simon Dominic HaynesJonathan Living
    • G06K9/00H04N5/235
    • G06K9/00248G06K9/00261G06K9/6255
    • Object detection apparatus for detecting objects in a test image comprises means for comparing blocks of a test window of the image with reference data indicative of the presence of an object to generate index figures indicative of a degree of similarity between a region and the reference data; means for storing probability data corresponding to possible values of the index figure and the block position; means operable, in respect of a current block, for accessing a probability value from the storing means in dependence on that block's position within the test window and the index figure generated in respect of that block; and means for combining the probability values corresponding to blocks in a test window to generate a result indicative of the probability of that test window containing an object; in which the probability values in the storing means are ordered by block position then by index figure.
    • 用于检测测试图像中的对象的对象检测装置包括用于将图像的测试窗口的块与指示对象存在的参考数据进行比较以产生指示区域与参考数据之间的相似程度的索引数据的装置; 用于存储对应于索引图和块位置的可能值的概率数据的装置; 关于当前块可用于根据该块在测试窗口内的位置和相对于该块生成的索引图形从存储装置访问概率值的装置; 以及用于将对应于块的概率值组合在测试窗口中以产生指示包含对象的测试窗口的概率的结果的装置; 其中存储装置中的概率值由块位置然后由索引数字排序。
    • 9. 发明授权
    • Reconfigurable multiplier array
    • 可重构的乘法器阵列
    • US06369610B1
    • 2002-04-09
    • US09582541
    • 2000-10-10
    • Peter Ying Kay CheungSimon Dominic Haynes
    • Peter Ying Kay CheungSimon Dominic Haynes
    • G06F738
    • G06F7/5324H03K19/17728H03K19/17732
    • This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.
    • 本发明提供了一种逻辑块,其包括部分计算电路(其中m> = 2和n> = 2)的m×n阵列,其可操作以产生m位被乘数x n位乘法和二进制乘法的部分乘积分量,并产生累积 一个被乘数的每个位的部分乘积的和。 一种可配置的输出电路,其可以在配置信号的控制下操作,(a)将由部分计算电路产生的部分乘积的累加和相加以产生乘积值,或(b)传递表示累积 在一个或多个另外的逻辑块内部分产品分量与部分计算电路的和。 还提供了包括两个或更多个这样的逻辑块的逻辑电路,用于逻辑块之间的数据传输的数据互连和用于控制信号传送到逻辑块的控制互连。