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1. 发明授权

US06369610B1 Reconfigurable multiplier array 失效
标题翻译：可重构的乘法器阵列
公开(公告)号：US06369610B1
公开(公告)日：2002-04-09
申请号：US09582541
申请日：2000-10-10
申请人： Peter Ying Kay Cheung , Simon Dominic Haynes
发明人： Peter Ying Kay Cheung , Simon Dominic Haynes
IPC分类号： G06F738
CPC分类号： G06F7/5324 , H03K19/17728 , H03K19/17732
摘要： This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.
摘要翻译：本发明提供了一种逻辑块，其包括部分计算电路（其中m> = 2和n> = 2）的m×n阵列，其可操作以产生m位被乘数x n位乘法和二进制乘法的部分乘积分量，并产生累积一个被乘数的每个位的部分乘积的和。一种可配置的输出电路，其可以在配置信号的控制下操作，（a）将由部分计算电路产生的部分乘积的累加和相加以产生乘积值，或（b）传递表示累积在一个或多个另外的逻辑块内部分产品分量与部分计算电路的和。还提供了包括两个或更多个这样的逻辑块的逻辑电路，用于逻辑块之间的数据传输的数据互连和用于控制信号传送到逻辑块的控制互连。

2. 发明申请

US20100180246A1 RANDOM GENERATION OF PLD CONFIGURATIONS TO COMPENSATE FOR DELAY VARIABILITY 审中-公开
标题翻译：随机生成PLD配置以补偿延迟变化
公开(公告)号：US20100180246A1
公开(公告)日：2010-07-15
申请号：US12526927
申请日：2008-02-15
申请人： Peter Ying Kay Cheung , Nicholas Peter Sedcole
发明人： Peter Ying Kay Cheung , Nicholas Peter Sedcole
IPC分类号： G06F17/50 , G06F7/58
CPC分类号： G06F17/5054 , H03K19/1731 , H03K19/17764
摘要： A method of generating a user circuit implementation for programming a PLD comprising generating a set of user circuit implementation configuration candidates, measuring one or more characteristics of the PLD in a measurement phase and selecting a user circuit implementation from the set of candidates based on a measured characteristic.
摘要翻译：一种产生用于对PLD进行编程的用户电路实现的方法，包括生成一组用户电路实现配置候选，测量测量阶段中的PLD的一个或多个特性，并且基于所测量的候选对象从候选组中选择用户电路实现特性。

3. 发明授权

US08552740B2 Method of measuring delay in an integrated circuit 有权
标题翻译：测量集成电路延迟的方法
公开(公告)号：US08552740B2
公开(公告)日：2013-10-08
申请号：US12747650
申请日：2008-12-10
申请人： Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung-Jit Wong
发明人： Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung-Jit Wong
IPC分类号： G01R23/12 , G01R23/175 , G06F19/00
CPC分类号： G01R31/31725
摘要： A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
摘要翻译：一种测量集成电路中的信号延迟的方法，包括在电路输入和输出处施加公共时钟信号，在电路输入处施加测试信号，检测电路输出端的相应输出信号，并检测测试信号和输出信号发生在时钟信号的公共部分。

4. 发明申请

US20110095768A1 METHOD OF MEASURING DELAY IN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中测量延迟的方法
公开(公告)号：US20110095768A1
公开(公告)日：2011-04-28
申请号：US12747650
申请日：2008-12-10
申请人： Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung Wong
发明人： Peter Ying Kay Cheung , Nicholas Peter Sedcole , Justin Sung Wong
IPC分类号： G01R27/28 , G06F17/50
CPC分类号： G01R31/31725
摘要： A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
摘要翻译：一种测量集成电路中的信号延迟的方法，包括在电路输入和输出处施加公共时钟信号，在电路输入处施加测试信号，检测电路输出端的相应输出信号，并检测测试信号和输出信号发生在时钟信号的公共部分。

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