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1. 发明授权

US07816253B2 Surface treatment of inter-layer dielectric 有权
标题翻译：层间电介质的表面处理
公开(公告)号：US07816253B2
公开(公告)日：2010-10-19
申请号：US11308422
申请日：2006-03-23
申请人： Shyng-Tsong Chen , Qinghuang Lin , Kelly Malone , Sanjay Mehta , Terry A. Spooner , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Qinghuang Lin , Kelly Malone , Sanjay Mehta , Terry A. Spooner , Chih-Chao Yang
IPC分类号： H01L21/76 , H01L21/425 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/3105 , H01L21/31058 , H01L21/76808 , H01L21/76814 , H01L21/76831
摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
摘要翻译：当在多孔超低k（ULK）材料上构建互连结构时，沟槽和/或通孔的底部通常被以下金属化工艺损坏，这可能适合于较高的介电材料。本发明的实施例可以提供在层间电介质（ILD）材料上形成互连结构的方法。该方法包括处理所述ILD材料的暴露区域以产生致密化区域以及金属化所述致密化区域的步骤。

2. 发明申请

US20080315347A1 PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS 审中-公开
标题翻译：提供覆盖层的GAPS以降低集成电路的BEOL制造的拉伸应力
公开(公告)号：US20080315347A1
公开(公告)日：2008-12-25
申请号：US11767789
申请日：2007-06-25
申请人： Griselda Bonilla , Shyng-Tsong Chen , Ronald A. DellaGuardia , Qinghuang Lin , Kelly Malone , Shom S. Ponoth , Chih-Chao Yang
发明人： Griselda Bonilla , Shyng-Tsong Chen , Ronald A. DellaGuardia , Qinghuang Lin , Kelly Malone , Shom S. Ponoth , Chih-Chao Yang
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/31695 , H01L21/02107 , H01L21/02203 , H01L21/7682 , H01L21/76825 , H01L21/76829 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit.
摘要翻译：使用包括一个或多个间隙或空隙的盖层来制造集成电路。在对与盖层相邻的层间电介质（ILD）层进行沉积和固化之前，提供间隙或空隙。间隙或空隙通过允许应力松弛减小并防止拉伸应力累积，从而防止集成电路的灾难性故障。

3. 发明申请

US20070222081A1 SURFACE TREATMENT OF INTER-LAYER DIELECTRIC 有权
标题翻译：层间电介质的表面处理
公开(公告)号：US20070222081A1
公开(公告)日：2007-09-27
申请号：US11308422
申请日：2006-03-23
申请人： Shyng-Tsong Chen , Qinghung Lin , Kelly Malone , Sanjay Mehta , Terry Spooner , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Qinghung Lin , Kelly Malone , Sanjay Mehta , Terry Spooner , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/76825 , H01L21/3105 , H01L21/31058 , H01L21/76808 , H01L21/76814 , H01L21/76831
摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
摘要翻译：当在多孔超低k（ULK）材料上构建互连结构时，沟槽和/或通孔的底部通常被以下金属化工艺损坏，这可能适合于较高的介电材料。本发明的实施例可以提供在层间电介质（ILD）材料上形成互连结构的方法。该方法包括处理所述ILD材料的暴露区域以产生致密化区域以及金属化所述致密化区域的步骤。

4. 发明授权

US08232195B2 Method for fabricating back end of the line structures with liner and seed materials 失效
标题翻译：用衬里和种子材料制造线结构后端的方法
公开(公告)号：US08232195B2
公开(公告)日：2012-07-31
申请号：US12137875
申请日：2008-06-12
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76865
摘要： A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.
摘要翻译：用于实现沉积在线（BEOL）互连结构的中间后端的表面或场上的减薄的贵金属衬里层的溅射蚀刻方法。贵金属衬里层基本上变薄到贵金属的作用在化学机械抛光（CMP）工艺中没有显着影响的程度。可以通过溅射蚀刻完全去除贵金属衬里层，以便通过化学机械抛光发生有效的平坦化。

5. 发明授权

US07402883B2 Back end of the line structures with liner and noble metal layer 有权
标题翻译：具有衬垫和贵金属层的线结构的后端
公开(公告)号：US07402883B2
公开(公告)日：2008-07-22
申请号：US11380074
申请日：2006-04-25
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L23/48
CPC分类号： H01L21/76846 , H01L21/76865
摘要： A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed between two surfaces of a dielectric material, wherein the first liner layer is in direct contact with at least a portion of a conductive wiring material of an underneath interconnect layer; a noble metal layer disposed on the first liner layer at least in the opening; and a conductive wiring material disposed on the noble metal layer, the conductive wiring material substantially filling the opening; wherein the first liner layer, the noble metal layer and the conductive wiring material are coplanar with the two surfaces of the dielectric material of the intermediate interconnect structure, and the noble metal layer includes a different material than the first liner layer.
摘要翻译：提出了半导体器件的线路（BEOL）结构的后端。在一个实施例中，该结构可以包括设置在中间互连结构上的第一衬里层，所述中间互连结构具有设置在电介质材料的两个表面之间的开口，其中第一衬垫层与至少一部分下面的互连层的导电布线材料; 至少在所述开口中设置在所述第一衬垫层上的贵金属层; 以及布置在所述贵金属层上的导电布线材料，所述导电布线材料基本上填充所述开口; 其中所述第一衬里层，所述贵金属层和所述导电布线材料与所述中间互连结构的介电材料的两个表面共面，并且所述贵金属层包括与所述第一衬里层不同的材料。

6. 发明申请

US20080242082A1 METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS 失效
标题翻译：用衬里和种子材料制作线结构的后端的方法
公开(公告)号：US20080242082A1
公开(公告)日：2008-10-02
申请号：US12137875
申请日：2008-06-12
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L21/768
CPC分类号： H01L21/76846 , H01L21/76865
摘要： A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.
摘要翻译：用于实现沉积在线（BEOL）互连结构的中间后端的表面或场上的减薄的贵金属衬里层的溅射蚀刻方法。贵金属衬里层基本上变薄到贵金属的作用在化学机械抛光（CMP）工艺中没有显着影响的程度。可以通过溅射蚀刻完全去除贵金属衬里层，以便通过化学机械抛光发生有效的平坦化。

7. 发明申请

US20070284736A1 ENHANCED MECHANICAL STRENGTH VIA CONTACTS 有权
标题翻译：通过联系增强机械强度
公开(公告)号：US20070284736A1
公开(公告)日：2007-12-13
申请号：US11419077
申请日：2006-05-18
申请人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
发明人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76844 , H01L21/76847 , H01L21/76877 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.
摘要翻译：本发明提供了一种改进的可靠性的互连结构。本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。嵌入的金属衬垫可以是连续的或不连续的。不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

8. 发明授权

US07671470B2 Enhanced mechanical strength via contacts 失效
公开(公告)号：US07671470B2
公开(公告)日：2010-03-02
申请号：US12179057
申请日：2008-07-24
申请人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
发明人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
IPC分类号： H01L21/461
CPC分类号： H01L23/5226 , H01L21/76844 , H01L21/76847 , H01L21/76877 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

9. 发明申请

US20080284030A1 ENHANCED MECHANICAL STRENGTH VIA CONTACTS 失效
标题翻译：通过联系增强机械强度
公开(公告)号：US20080284030A1
公开(公告)日：2008-11-20
申请号：US12179057
申请日：2008-07-24
申请人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
发明人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76844 , H01L21/76847 , H01L21/76877 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.
摘要翻译：本发明提供了一种改进的可靠性的互连结构。本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。嵌入的金属衬垫可以是连续的或不连续的。不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

10. 发明授权

US07670943B2 Enhanced mechanical strength via contacts 失效
标题翻译：通过触点增强机械强度
公开(公告)号：US07670943B2
公开(公告)日：2010-03-02
申请号：US12179054
申请日：2008-07-24
申请人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
发明人： Chih-Chao Yang , Griselda Bonilla , Shyng-Tsong Chen , Kelly Malone
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76844 , H01L21/76847 , H01L21/76877 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.
摘要翻译：本发明提供了一种改进的可靠性的互连结构。本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。嵌入的金属衬垫可以是连续的或不连续的。不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

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