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1. 发明授权

US08638618B2 Decoder for NAND memory 有权
标题翻译： NAND存储器解码器
公开(公告)号：US08638618B2
公开(公告)日：2014-01-28
申请号：US13185887
申请日：2011-07-19
申请人： Shuo-Nan Hung , Chang Ting Chen , Chi-Yu Hung , Tseng-Yi Liu
发明人： Shuo-Nan Hung , Chang Ting Chen , Chi-Yu Hung , Tseng-Yi Liu
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C13/0028 , G11C16/0483 , G11C16/08 , G11C16/12
摘要： An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.
摘要翻译：集成电路器件具有多块NAND存储器单元和高压开关。高电压开关耦合到解码器输出和NAND存储器单元的块。高压开关具有正负电压的输出电压范围。

2. 发明申请

US20120163087A1 Decoder for Nand Memory 有权
标题翻译： Nand Memory的解码器
公开(公告)号：US20120163087A1
公开(公告)日：2012-06-28
申请号：US13185887
申请日：2011-07-19
申请人： Shuo-Nan Hung , Chang Ting Chen , Chi-Yu Hung , Tseng-Yi Liu
发明人： Shuo-Nan Hung , Chang Ting Chen , Chi-Yu Hung , Tseng-Yi Liu
IPC分类号： G11C16/08
CPC分类号： G11C8/10 , G11C13/0028 , G11C16/0483 , G11C16/08 , G11C16/12
摘要： An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.
摘要翻译：集成电路器件具有多块NAND存储器单元和高压开关。高电压开关耦合到解码器输出和NAND存储器单元的块。高压开关具有正负电压的输出电压范围。

3. 发明授权

US08526235B2 Method and apparatus for reducing read disturb in memory 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US08526235B2
公开(公告)日：2013-09-03
申请号：US13406215
申请日：2012-02-27
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.
摘要翻译： NAND存储器的各个方面包括具有高阈值电压分布的多个版本 - 具有减小的最大值的版本和另一版本。具有减小的最大值的版本具有减小的字线通过电压。

4. 发明申请

US20120155181A1 Method and Apparatus for Reducing Read Disturb in Memory 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US20120155181A1
公开(公告)日：2012-06-21
申请号：US13406215
申请日：2012-02-27
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/26
CPC分类号： G11C16/10
摘要： Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.
摘要翻译： NAND存储器的各个方面包括具有高阈值电压分布的多个版本 - 具有减小的最大值的版本和另一版本。具有减小的最大值的版本具有减小的字线通过电压。

5. 发明授权

US08527839B2 On-the-fly repair method for memory 有权
标题翻译：内存的动态修复方法
公开(公告)号：US08527839B2
公开(公告)日：2013-09-03
申请号：US13017372
申请日：2011-01-31
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C29/00
CPC分类号： G11C29/82
摘要： An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set.
摘要翻译：一种用于存储器的动态修复方法包括：对存储器执行块擦除操作; 检查块擦除操作是否通过; 如果块擦除操作未通过，查找存储器中是否存在任何可用且健康的冗余块; 将要修复的故障块的地址，使能位和至少一个纠错位编程到存储器的冗余信息集中的第一和第二冗余信息区; 基于纠错位检查第一和第二冗余信息区域中的错误是否可恢复; 并且如果可恢复该错误，则将冗余信息设置为有效以将故障块替换为与有效冗余信息集相关的冗余块。

6. 发明申请

US20120198298A1 On-the-Fly Repair Method for Memory 有权
标题翻译：内存修复方法
公开(公告)号：US20120198298A1
公开(公告)日：2012-08-02
申请号：US13017372
申请日：2011-01-31
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G06F11/14
CPC分类号： G11C29/82
摘要： An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set.
摘要翻译：一种用于存储器的动态修复方法包括：对存储器执行块擦除操作; 检查块擦除操作是否通过; 如果块擦除操作未通过，查找存储器中是否存在任何可用且健康的冗余块; 将要修复的故障块的地址，使能位和至少一个纠错位编程到存储器的冗余信息集中的第一和第二冗余信息区; 基于纠错位检查第一和第二冗余信息区域中的错误是否可恢复; 并且如果可恢复该错误，则将冗余信息设置为有效以将故障块替换为与有效冗余信息集相关的冗余块。

7. 发明授权

US08149624B1 Method and apparatus for reducing read disturb in memory 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US08149624B1
公开(公告)日：2012-04-03
申请号：US12878358
申请日：2010-09-09
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.
摘要翻译： NAND存储器的各个方面包括具有高阈值电压分布的多个版本 - 具有减小的最大值的版本和另一版本。具有减小的最大值的版本具有减小的字线通过电压。

8. 发明申请

US20120063232A1 METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US20120063232A1
公开(公告)日：2012-03-15
申请号：US12878358
申请日：2010-09-09
申请人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.
摘要翻译： NAND存储器的各个方面包括具有高阈值电压分布的多个版本 - 具有减小的最大值的版本和另一版本。具有减小的最大值的版本具有减小的字线通过电压。

9. 发明授权

US08625343B2 Method and apparatus for reducing read disturb in memory 有权
公开(公告)号：US08625343B2
公开(公告)日：2014-01-07
申请号：US12878299
申请日：2010-09-09
申请人： Chung-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chung-Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.

10. 发明申请

US20120063236A1 Method and Apparatus for Reducing Read Disturb in Memory 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US20120063236A1
公开(公告)日：2012-03-15
申请号：US12878299
申请日：2010-09-09
申请人： Chun Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
发明人： Chun Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
摘要翻译： NAND存储器的各个方面包括控制电路，该控制电路通过测量在串联的第一端和第二端之间流动的电流来将读偏置装置施加到多个字线以读取存储在多个存储单元上的选定数据值的记忆细胞。读取偏置布置被施加到多个字线的字线仅施加小于第二阈值电压分布的第二最大值的字线电压。

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