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1. 发明授权

US07187961B2 Semiconductor device for sensor system 失效
标题翻译：传感器系统半导体器件
公开(公告)号：US07187961B2
公开(公告)日：2007-03-06
申请号：US10457498
申请日：2003-06-10
申请人： Shunzo Yamashita , Kei Suzuki , Toshiyuki Aritsuka , Masayuki Miyazaki , Sadaki Nakano
发明人： Shunzo Yamashita , Kei Suzuki , Toshiyuki Aritsuka , Masayuki Miyazaki , Sadaki Nakano
IPC分类号： A61B5/00
CPC分类号： A61B5/0002 , A61B5/02055 , A61B5/02427 , A61B5/0531 , A61B5/11 , A61B5/7232 , A61B2560/0209 , A61B2560/0412 , A61B2562/0219 , A61B2562/028 , A61B2562/08 , G01D9/005 , G01K7/01 , G01K2215/00 , G01P15/125 , G01P2015/0814 , H01L35/32 , H01L2924/0002 , Y10S128/903 , H01L2924/00
摘要： A semiconductor device is employable for a compact and light-weight sensor system that is free of the need for battery replacement. The semiconductor device has a sensor chip (SCHIP1) comprising sensors (TD1, AS1, PD1, GS1), an A/D conversion circuit (AD1), a microprocessor (CPU1), a memory (MEM1), a transmission circuit (RF1), and a power generation circuit (CM1). The sensors, the A/D conversion circuit, the microprocessor, the memory, and the transmission circuit are formed on one side (SIDE1) of a substrate, while the power generation unit is formed on the other side (SIDE2) of the substrate.
摘要翻译：半导体器件可用于紧凑且轻量的传感器系统，其不需要更换电池。半导体器件具有传感器芯片（SCHIP1），包括传感器（TD1，AS1，PD1，GS1），A / D转换电路（AD 1），微处理器（CPU 1），存储器），发送电路（RF 1）和发电电路（CM 1）。传感器，A / D转换电路，微处理器，存储器和传输电路形成在衬底的一侧（SIDE 1）上，而发电单元形成在衬底的另一侧（SIDE 2）上基质。

2. 发明授权

US06950767B2 Quality monitoring system for building structure, quality monitoring method for building structure and semiconductor integrated circuit device 失效
标题翻译：建筑结构质量监测系统，建筑结构质量监测方法和半导体集成电路装置
公开(公告)号：US06950767B2
公开(公告)日：2005-09-27
申请号：US10706972
申请日：2003-11-14
申请人： Shunzo Yamashita , Kei Suzuki , Toshiyuki Aritsuka , Sadaki Nakano
发明人： Shunzo Yamashita , Kei Suzuki , Toshiyuki Aritsuka , Sadaki Nakano
IPC分类号： G01N33/38 , G06F19/00
CPC分类号： G01N33/383
摘要： A low cost system and method are provided for long-term monitoring of the quality of a building structure utilizing a semiconductor integrated circuit device buried in the structure. A monitoring chip includes a sensor, a microprocessor, a memory, a radio interface, an electric power controller and an electric power generator. The monitoring chip intermittently receives power to intermittently monitor information such as whether concrete is adequately cured, whether the quantity of moisture and chloride ions in concrete paste is adequate, or whether a state of stress inside concrete is in question. Temperature sensors, electric resistance sensors and pressure sensors respectively built in the monitoring chip use the built-in electric power generator as a power source, and the system store any abnormal measured values in a built-in memory. Collected quality data is transmitted according to an external request to indicate building structure quality.
摘要翻译：提供了一种低成本的系统和方法，用于利用埋在结构中的半导体集成电路器件长期监测建筑结构的质量。监视芯片包括传感器，微处理器，存储器，无线电接口，电力控制器和发电机。监控芯片间歇地接收电力以间歇地监测混凝土浆料中的水分和氯离子的量是否足够，混凝土内部的应力状态是否有问题的信息。分别内置在监控芯片中的温度传感器，电阻传感器和压力传感器使用内置发电机作为电源，并将内部存储器中的任何异常测量值存储。收集的质量数据根据外部要求传输，以指示建筑结构质量。

3. 发明授权

US08898189B2 Database management method, computer, sensor network system and time-series data management method 有权
标题翻译：数据库管理方法，计算机，传感器网络系统和时间序列数据管理方法
公开(公告)号：US08898189B2
公开(公告)日：2014-11-25
申请号：US13583108
申请日：2010-07-22
申请人： Sadaki Nakano , Keiro Muro , Shinji Fujiwara
发明人： Sadaki Nakano , Keiro Muro , Shinji Fujiwara
IPC分类号： G06F17/30 , G05B23/02
CPC分类号： G05B23/0283 , G06F17/30424 , G06F17/30548
摘要： In a system manages a plurality of pieces of sensor information in a plant, or the like, it can be reducing an amount of data stored in a database and easily a processing for searching a place of an anomaly and an anomaly cause.A database management method for use in a computer for managing a database, the database management method including: a step of analyzing a query; a step of generating a first inquiry for searching the database for compressed data; a step of generating a second inquiry for executing a search of time-series data; a step of extracting given data from the obtained time-series data, based on a response result of the second inquiry; and a step of generating an output result by extracting data to be output to a client computer from the given data.
摘要翻译：在系统中管理工厂中的多条传感器信息等时，可以减少存储在数据库中的数据量，并且容易地进行搜索异常处所和异常原因的处理。一种用于计算机中用于管理数据库的数据库管理方法，所述数据库管理方法包括：分析查询的步骤; 生成用于搜索数据库的压缩数据的第一查询的步骤; 生成用于执行时间序列数据的搜索的第二查询的步骤; 基于所述第二查询的响应结果从所获得的时间序列数据中提取给定数据的步骤; 以及通过从给定数据提取要输出到客户端计算机的数据来生成输出结果的步骤。

4. 发明授权

US5918045A Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US5918045A
公开(公告)日：1999-06-29
申请号：US953387
申请日：1997-10-17
申请人： Osamu Nishii , Sadaki Nakano , Norio Nakagawa , Takanobu Tsunoda
发明人： Osamu Nishii , Sadaki Nakano , Norio Nakagawa , Takanobu Tsunoda
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/324 , G06F9/3804 , G06F9/3842
摘要： The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.
摘要翻译：数据处理器包括CPU和预取由CPU执行的指令并将其存储在其中的指令预取缓冲器。 CPU包含检测电路，用于根据相关分支指令保持的分支位移信息来检测从分支指令到分支目标指令的位移是否是特定位移。当检测电路检测到位移不是特定位移时，指令预取缓冲器清除已经预取的指令，并将新提取的分支目标指令输出到CPU，并且当检测电路检测到时，将已经预取的分支目标指令输出到CPU 位移是具体的位移。因此，日期处理器从指令预取缓冲器中以高速度在一定范围内提取分支目标指令，而不在指令代码上添加无效位。

5. 发明授权

US07178046B2 Halting clock signals to input and result latches in processing path upon fetching of instruction not supported 有权
标题翻译：在不支持指令的提取时，将时钟信号停止到处理路径中的输入和结果锁存器
公开(公告)号：US07178046B2
公开(公告)日：2007-02-13
申请号：US11095685
申请日：2005-04-01
申请人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
发明人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F8/4432 , G06F9/30083 , G06F9/30145 , G06F9/30156 , G06F9/3017 , G06F9/3877 , G06F9/3885 , Y02D10/128 , Y02D10/152 , Y02D10/171 , Y02D10/41
摘要： A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.
摘要翻译：微处理器包括第一高速缓冲存储器，第一指令提取单元，第一指令解码器，第一处理单元和保存从第一指令译码器输出的控制信号的第一锁存器。当第一指令提取单元接收到由第一处理单元执行的第一指令时，它向第一指令解码器输出第一指令。当第一指令提取单元接收到不由第一处理单元执行的第二指令时，它向第一指令解码器输出特定指令，之后向其他锁存电路提供时钟脉冲在第一处理单元中基于暂停对控制信号。

6. 发明申请

US20060114113A1 Gas detection system 有权
标题翻译：气体检测系统
公开(公告)号：US20060114113A1
公开(公告)日：2006-06-01
申请号：US11070460
申请日：2005-03-03
申请人： Koichi Yokosawa , Sadaki Nakano , Yasushi Goto
发明人： Koichi Yokosawa , Sadaki Nakano , Yasushi Goto
IPC分类号： G01N7/00
CPC分类号： G01N33/0063 , G01N27/123
摘要： A gas detection system capable of suppressing the power consumption of the system using gas sensors required for heating for measurement at high accuracy, comprising a server and a plurality of gas sensors connected by way of wireless communication with the server, in which each of the gas sensors is provided with a heater, a controller for controlling the ON-OFF for the power supply to the heater and a comparator for comparing the detected gas concentration with a predetermined threshold value. In the gas detection system, electric power is not usually supplied to the heater in each of the gas sensors and the gas sensor measures the gas concentration at a low accuracy and always compares it with the threshold value. In a case where the gas concentration exceeds the threshold value in one of the gas sensors, it turns the heater of its own to ON thereby switching the measurement to that at high accuracy and turns the heater to OFF upon completing the measurement. At the same time, it informs the detection for the excess of threshold value to the server and the server lowers the threshold value of the gas sensors in the vicinity of the gas sensor that has informed the detection for the excess of threshold value to make the monitoring level severer.
摘要翻译：一种气体检测系统，其能够以高精度抑制用于加热测量所需的气体传感器的系统的功率消耗，包括通过与服务器的无线通信连接的服务器和多个气体传感器，其中每个气体传感器设置有加热器，用于控制对加热器的电源的ON-OFF的控制器和用于将检测到的气体浓度与预定阈值进行比较的比较器。在气体检测系统中，通常不向每个气体传感器中的加热器供电，并且气体传感器以低精度测量气体浓度，并且始终将其与阈值进行比较。在其中一个气体传感器中气体浓度超过阈值的情况下，它将其自身的加热器变为ON，从而将测量值以高精度切换，并在完成测量时将加热器转为OFF。同时，它通知检测到服务器的阈值过大，服务器和服务器降低气体传感器附近的气体传感器的阈值，该气体传感器通知检测阈值超过阈值，监控级别更严重。

7. 发明申请

US20130205014A1 COMPUTER SYSTEM AND RULE GENERATION METHOD 有权
标题翻译：计算机系统和规则生成方法
公开(公告)号：US20130205014A1
公开(公告)日：2013-08-08
申请号：US13698163
申请日：2011-02-21
申请人： Keiro Muro , Sadaki Nakano
发明人： Keiro Muro , Sadaki Nakano
IPC分类号： H04L29/06
CPC分类号： H04L29/06891 , G05B23/0237 , G06Q10/06 , H04L67/12
摘要： Disclosed is a computer system provided with a plurality of sensors provided in a plurality of devices to observe a predetermined amount, and a server for examining the physical amount transmitted from the sensors, wherein the plurality of devices are classified into a first device group and a plurality of second device groups, a plurality of second examination rules indicating the examination methods of the physical amount are set in the plurality of second device groups, the server calculates the similarity between the first device group and each of the second device groups, and, on the basis of the calculated similarity, a first examination rule to be set in the first device group is extracted from the plurality of second examination rules set in the plurality of second device groups.
摘要翻译：公开了一种计算机系统，其具有设置在多个装置中的多个传感器以观察预定量;以及服务器，用于检查从传感器发送的物理量，其中多个装置分为第一装置组和第多个第二设备组，在多个第二设备组中设置指示物理量的检查方法的多个第二检查规则，服务器计算第一设备组与第二设备组之间的相似度，基于计算出的相似度，从在多个第二设备组中设置的多个第二检查规则中提取要在第一设备组中设置的第一检查规则。

8. 发明申请

US20060114114A1 Wireless terminal with gas leakage detection function, gas leakage detection system using the same, and gas leakage notification method 有权
标题翻译：无线终端具有气体泄漏检测功能，气体泄漏检测系统采用相同的气体泄漏检测方法
公开(公告)号：US20060114114A1
公开(公告)日：2006-06-01
申请号：US11181928
申请日：2005-07-15
申请人： Sadaki Nakano , Koichi Yokosawa , Yasushi Goto
发明人： Sadaki Nakano , Koichi Yokosawa , Yasushi Goto
IPC分类号： G08B17/10 , H04L12/26 , G08B1/08 , G08B21/00
CPC分类号： G08B25/08 , G08B21/16 , G08B21/182 , G08B25/007 , G08B25/10
摘要： In a hydrogen gas station where a great number of sensors are installed, in case hydrogen leakage occurs, sensors in the vicinity of the leakage location start to transmit warning to an access point all at once. This causes channel capacity saturation and failure to transmit warning to the access point. Nodes and the access point are connected each other by an uplink channel and a downlink channel. The access point detects congested/uncongested status of the uplink channel by using a wireless transmitter module and notifies the nodes of the congested/uncongested status of the channel by means for transmitting onto the downlink channel. Meanwhile, each node controls its transmission operation, according to the hydrogen concentration level detected by its hydrogen sensor and the uplink channel congested/uncongested status notified from the access point. In this way, channel overflow due to access congestion in case of hydrogen leakage can be prevented.
摘要翻译：在安装了大量传感器的氢气站中，在发生氢泄漏的情况下，泄漏位置附近的传感器开始一次性向接入点发送警告。这导致通道容量饱和，并且无法向接入点发送警告。节点和接入点通过上行链路信道和下行链路信道相互连接。接入点通过使用无线发射机模块来检测上行链路信道的拥塞/非占用状态，并通过传输到下行链路信道的方式向节点通知信道的拥塞/非占用状态。同时，每个节点根据其氢传感器检测到的氢浓度水平和从接入点通知的上行链路信道拥塞/非占用状态来控制其传输操作。以这种方式，可以防止在泄漏的情况下由于访问拥塞而导致的信道溢出。

9. 发明申请

US20050169086A1 Low power consumption microprocessor 有权
标题翻译：低功耗微处理器
公开(公告)号：US20050169086A1
公开(公告)日：2005-08-04
申请号：US11095685
申请日：2005-04-01
申请人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
发明人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
IPC分类号： G06F9/38 , G06F1/32 , G06F7/00 , G06F9/318 , G06F9/45 , G11C7/00
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F8/4432 , G06F9/30083 , G06F9/30145 , G06F9/30156 , G06F9/3017 , G06F9/3877 , G06F9/3885 , Y02D10/128 , Y02D10/152 , Y02D10/171 , Y02D10/41
摘要： A microprocessor including a first cache memory, a first instruction fetch unit coupled to the first cache memory, a first instruction decoder coupled to the first instruction fetch unit, and a first processing unit coupled to the first instruction decoder, wherein, when the first instruction fetch unit is inputted with a first instruction which is performed by the first processing unit, the first instruction fetch unit outputs the first instruction to the first instruction decoder, wherein when the first instruction fetch unit is inputted with a second instruction which is not performed by the first processing unit, the first instruction fetch unit outputs a specific instruction to the first instruction decoder, and wherein, in the case where the first instruction fetch unit outputs the specific instruction to the first instruction decoder, the supply of clock pulse to the first processing unit is halted.
摘要翻译：包括第一高速缓冲存储器，耦合到第一高速缓存存储器的第一指令提取单元，耦合到第一指令提取单元的第一指令解码器和耦合到第一指令解码器的第一处理单元的微处理器，其中当第一指令输入第一指令的第一指令由第一处理单元输入，第一指令提取单元向第一指令解码器输出第一指令，其中当第一指令提取单元输入第二指令时，第二指令不由第一指令执行，第一处理单元，第一指令获取单元向第一指令解码器输出特定指令，并且其中，在第一指令提取单元向第一指令解码器输出特定指令的情况下，向第一指令解码器提供时钟脉冲处理单元停止。

10. 发明授权

US06877087B1 Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving 有权
标题翻译：用NOP将指定的指令代入功能单元，并将时钟脉冲停止到数据锁存器进行省电
公开(公告)号：US06877087B1
公开(公告)日：2005-04-05
申请号：US09603965
申请日：2000-06-26
申请人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
发明人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
IPC分类号： G06F9/38 , G06F1/32 , G06F7/00 , G06F9/318 , G06F9/45
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F8/4432 , G06F9/30083 , G06F9/30145 , G06F9/30156 , G06F9/3017 , G06F9/3877 , G06F9/3885 , Y02D10/128 , Y02D10/152 , Y02D10/171 , Y02D10/41
摘要： A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.
摘要翻译：一种微处理器，用于减少浮点单元浪费的功耗。使用指令无效化逻辑电路来代替从指令高速缓冲存储器提供的指令串中的不使用浮点单元的指令与无效指令，将该无效指令保持在浮点寄存器中，并将该无效指令提供给浮点单元中的浮点解码器。在无效指令连续的情况下，浮点数据路径以及浮点解码器和浮点寄存器的功耗降低。

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