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1. 发明申请

US20060220192A1 Semiconductor substrate, substrate for semiconductor crystal growth, semiconductor device, optical semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体衬底，用于半导体晶体生长的衬底，半导体器件，光学半导体器件及其制造方法
公开(公告)号：US20060220192A1
公开(公告)日：2006-10-05
申请号：US11391200
申请日：2006-03-29
申请人： Shunsuke Kurachi , Tsutomu Komatani
发明人： Shunsuke Kurachi , Tsutomu Komatani
IPC分类号： H01L23/495
CPC分类号： H01L21/3185 , B82Y20/00 , H01L21/0217 , H01L21/02186 , H01L21/0237 , H01L21/02378 , H01L21/0254 , H01L21/02664 , H01L21/3143 , H01L21/31604 , H01L23/3171 , H01L29/2003 , H01L29/7787 , H01L2924/0002 , H01S5/0201 , H01S5/0207 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/34333 , H01S2301/173 , H01L2924/00
摘要： A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in the same direction as the direction of stress which the semiconductor crystal layer applies to the substrate. In this case, stress of the semiconductor crystal layer to the substrate is offset. Therefore, warp of the semiconductor substrate and generation of cracks are inhibited.
摘要翻译：半导体衬底包括：在衬底的一个面上生长的半导体晶体层; 以及应力松弛层，其形成在与所述基板的一个面和所述侧面相反的另一面上，并且在与所述基板的半导体晶体层施加的应力的方向相同的方向上对所述基板施加应力。在这种情况下，半导体晶体层对基板的应力被抵消。因此，抑制了半导体衬底的翘曲和裂纹的产生。

2. 发明授权

US08178900B2 Semiconductor device having GaN-based semiconductor layer and select composition ratio insulating film 有权
标题翻译：具有GaN基半导体层和选择组成比绝缘膜的半导体器件
公开(公告)号：US08178900B2
公开(公告)日：2012-05-15
申请号：US11392785
申请日：2006-03-30
申请人： Shunsuke Kurachi , Tsutomu Komatani
发明人： Shunsuke Kurachi , Tsutomu Komatani
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/812
摘要： A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, and an insulating film composed of any one of silicon nitride in which the composition ratio of silicon to nitrogen is 0.85 to 3.0, silicon oxide in which the composition ratio of silicon to oxygen is 0.6 to 3.0, or silicon oxide nitride in which the composition ratio of silicon to nitrogen and oxygen is 0.6 to 3.0 that is formed on a surface of the GaN-based semiconductor layer, a gate electrode formed on the GaN-based semiconductor layer, and a source electrode and a drain electrode formed with the gate electrode therebetween.
摘要翻译：半导体器件包括在基板上形成的GaN基半导体层和由硅与氮的组成比为0.85〜3.0的氮化硅构成的绝缘膜，硅与硅的组成比为氧为0.6〜3.0，或者在GaN系半导体层的表面上形成的硅与氮和氧的组成比为0.6〜3.0的氧化硅氮化物，形成在GaN系半导体层上的栅电极以及在其间形成有栅电极的源电极和漏电极。

3. 发明申请

US20060220063A1 Semiconductor device having GaN-based semiconductor layer 有权
标题翻译：具有GaN基半导体层的半导体器件
公开(公告)号：US20060220063A1
公开(公告)日：2006-10-05
申请号：US11392785
申请日：2006-03-30
申请人： Shunsuke Kurachi , Tsutomu Komatani
发明人： Shunsuke Kurachi , Tsutomu Komatani
IPC分类号： H01L29/739
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/812
摘要： A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, and an insulating film composed of any one of silicon nitride in which the composition ratio of silicon to nitrogen is 0.85 to 3.0, silicon oxide in which the composition ratio of silicon to oxygen is 0.6 to 3.0, or silicon oxide nitride in which the composition ratio of silicon to nitrogen and oxygen is 0.6 to 3.0 that is formed on a surface of the GaN-based semiconductor layer, a gate electrode formed on the GaN-based semiconductor layer, and a source electrode and a drain electrode formed with the gate electrode therebetween.
摘要翻译：半导体器件包括在基板上形成的GaN基半导体层和由硅与氮的组成比为0.85〜3.0的氮化硅构成的绝缘膜，硅与硅的组成比为氧为0.6〜3.0，或者在GaN系半导体层的表面上形成的硅与氮和氧的组成比为0.6〜3.0的氧化硅氮化物，形成在GaN系半导体层上的栅电极以及在其间形成有栅电极的源电极和漏电极。

4. 发明授权

US07442999B2 Semiconductor substrate, substrate for semiconductor crystal growth, semiconductor device, optical semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体衬底，用于半导体晶体生长的衬底，半导体器件，光学半导体器件及其制造方法
公开(公告)号：US07442999B2
公开(公告)日：2008-10-28
申请号：US11391200
申请日：2006-03-29
申请人： Shunsuke Kurachi , Tsutomu Komatani
发明人： Shunsuke Kurachi , Tsutomu Komatani
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/3185 , B82Y20/00 , H01L21/0217 , H01L21/02186 , H01L21/0237 , H01L21/02378 , H01L21/0254 , H01L21/02664 , H01L21/3143 , H01L21/31604 , H01L23/3171 , H01L29/2003 , H01L29/7787 , H01L2924/0002 , H01S5/0201 , H01S5/0207 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/34333 , H01S2301/173 , H01L2924/00
摘要： A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in the same direction as the direction of stress which the semiconductor crystal layer applies to the substrate. In this case, stress of the semiconductor crystal layer to the substrate is offset. Therefore, warp of the semiconductor substrate and generation of cracks are inhibited.
摘要翻译：半导体衬底包括：在衬底的一个面上生长的半导体晶体层; 以及应力松弛层，其形成在与所述基板的一个面和所述侧面相反的另一面上，并且在与所述基板的半导体晶体层施加的应力的方向相同的方向上对所述基板施加应力。在这种情况下，半导体晶体层对基板的应力被抵消。因此，抑制了半导体衬底的翘曲和裂纹的产生。

5. 发明申请

US20110081784A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20110081784A1
公开(公告)日：2011-04-07
申请号：US12893481
申请日：2010-09-29
申请人： Toshiyuki Kosaka , Haruo Kawata , Tsutomu Komatani
发明人： Toshiyuki Kosaka , Haruo Kawata , Tsutomu Komatani
IPC分类号： H01L21/033
CPC分类号： H01L21/0475 , H01L21/3081 , H01L21/76898 , H01L21/78 , H01L29/2003 , H01L29/812
摘要： A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.
摘要翻译：半导体器件的制造方法包括：在基板的第二主面上形成蚀刻掩模的形成步骤，所述蚀刻掩模由Cu或Cu合金制成并具有开口，所述第二主面位于设置有氮化物半导体层的基板的第一主面; 使用蚀刻掩模对基板的第二主面施加干蚀刻以留下氮化物半导体层的全部或一部分的第一蚀刻步骤; 在第一蚀刻步骤之后去除蚀刻掩模的去除步骤; 以及在去除步骤之后干蚀刻左氮化物半导体层的第二蚀刻步骤。

6. 发明申请

US20050250336A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050250336A1
公开(公告)日：2005-11-10
申请号：US11125137
申请日：2005-05-10
申请人： Tsutomu Komatani
发明人： Tsutomu Komatani
IPC分类号： H01L21/28 , H01L21/00 , H01L21/033 , H01L21/04 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/338 , H01L21/461 , H01L21/768 , H01L29/778 , H01L29/812
CPC分类号： H01L21/3086 , H01L21/0332 , H01L21/0475 , H01L21/3081
摘要： A method of fabricating a semiconductor device includes forming a film stack having a Ti film and a metal film containing Ni sequentially deposited on a surface of a substrate of a GaN based semiconductor, SiC, or sapphire, patterning the film stack to expose a portion of the surface of the etching substance, and dry etching an exposed portion of the surface of the etching substance. It is thus possible to enhance the adhesion between a dry etching mask and the surface of the etching substance. Peeling and cracking are suppressed and the highly accurate etching can be performed.
摘要翻译：一种制造半导体器件的方法包括：形成具有Ti膜的金属膜和依次沉积在GaN基半导体，SiC或蓝宝石的衬底的表面上的Ni的膜堆叠，蚀刻物质的表面，并且干蚀刻蚀刻物质的表面的暴露部分。因此，可以提高干蚀刻掩模与蚀刻物质的表面之间的粘附性。剥离和破裂被抑制，并且可以执行高精度的蚀刻。

7. 发明申请

US20080087634A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20080087634A1
公开(公告)日：2008-04-17
申请号：US11872224
申请日：2007-10-15
申请人： Toshiyuki Kohsaka , Tsutomu Komatani
发明人： Toshiyuki Kohsaka , Tsutomu Komatani
IPC分类号： B44C1/22
CPC分类号： H01L21/0445 , H01L21/0332 , H01L21/76898
摘要： A manufacturing method of a semiconductor device includes forming a metal mask on a substrate or on a layer provided on the substrate, and removing at least one of the substrate and the layer provided on the substrate selectively through a dry etching treatment with use of the metal mask. The metal mask has a first open pattern and a second open pattern. The first open pattern is opened at a given area of the metal pattern. The second open pattern is opened at an area dividing the metal mask.
摘要翻译：半导体器件的制造方法包括在衬底上或设置在衬底上的层上形成金属掩模，并且通过使用金属的干蚀刻处理选择性地去除衬底和设置在衬底上的层中的至少一个面具。金属掩模具有第一打开图案和第二打开图案。在金属图案的给定区域处打开第一开放图案。在划分金属掩模的区域处打开第二打开图案。

8. 发明授权

US08476166B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08476166B2
公开(公告)日：2013-07-02
申请号：US12893481
申请日：2010-09-29
申请人： Toshiyuki Kosaka , Haruo Kawata , Tsutomu Komatani
发明人： Toshiyuki Kosaka , Haruo Kawata , Tsutomu Komatani
IPC分类号： H01L21/311
CPC分类号： H01L21/0475 , H01L21/3081 , H01L21/76898 , H01L21/78 , H01L29/2003 , H01L29/812
摘要： A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.
摘要翻译：半导体器件的制造方法包括：在基板的第二主面上形成蚀刻掩模的形成步骤，所述蚀刻掩模由Cu或Cu合金制成并具有开口，所述第二主面位于设置有氮化物半导体层的基板的第一主面; 使用蚀刻掩模对基板的第二主面施加干蚀刻以留下氮化物半导体层的全部或一部分的第一蚀刻步骤; 在第一蚀刻步骤之后去除蚀刻掩模的去除步骤; 以及在去除步骤之后干蚀刻左氮化物半导体层的第二蚀刻步骤。

9. 发明申请

US20050236365A1 Dry etching method and semiconductor device 审中-公开
标题翻译：干蚀刻法和半导体器件
公开(公告)号：US20050236365A1
公开(公告)日：2005-10-27
申请号：US11115272
申请日：2005-04-27
申请人： Tsutomu Komatani
发明人： Tsutomu Komatani
IPC分类号： H01L21/3065 , H01L21/00 , H01L21/306 , H01L21/311 , H01L21/335 , H01L21/338 , H01L29/20 , H01L29/778 , H01L29/812
CPC分类号： H01L29/66462 , H01L21/30621 , H01L21/31116 , H01L29/2003
摘要： A method of dry etching an etching layer that coats a surface of a GaN based semiconductor layer or a SiC, the method includes performing a first plasma etching to remain a desired thickness of the etching layer, and performing a second plasma etching on a region remained by the first plasma etching with a lower energy than that of the first plasma etching to expose a surface of the GaN based semiconductor layer or the SiC. The method of dry etching of the present invention is capable of suppressing the damage on the GaN based semiconductor layer and thereby achieving the dry etching method of the high selectivity, high anisotropy, low contamination, and low damage. It is thus possible to achieve the GaN based semiconductor device having excellent initial device characteristics and free from degradation due to conduction.
摘要翻译：一种干法蚀刻涂覆GaN基半导体层或SiC的表面的蚀刻层的方法，该方法包括进行第一等离子体蚀刻以保持蚀刻层的所需厚度，并且对所保留的区域进行第二等离子体蚀刻通过用比第一等离子体蚀刻的能量低的第一等离子体蚀刻来暴露GaN基半导体层或SiC的表面。本发明的干蚀刻方法能够抑制GaN基半导体层的损伤，从而实现高选择性，高各向异性，低污染和低损伤的干蚀刻方法。因此，可以实现具有优异的初始器件特性并且不会由于导通而劣化的GaN基半导体器件。

10. 发明申请

US20050221628A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050221628A1
公开(公告)日：2005-10-06
申请号：US11093238
申请日：2005-03-30
申请人： Masahiro Tanaka , Tsutomu Komatani
发明人： Masahiro Tanaka , Tsutomu Komatani
IPC分类号： H01L21/318 , H01L21/338 , H01L21/8242 , H01L29/20 , H01L29/51 , H01L29/778 , H01L29/812 , H01L33/06 , H01L33/32 , H01L33/44
CPC分类号： H01L29/51 , H01L29/2003 , H01L29/7787
摘要： A semiconductor device includes a silicon nitride (SiN) film provided on a crystal surface of a nitride semiconductor, the SiN film having a hydrogen content equal to or smaller than 15 percent.
摘要翻译：半导体器件包括设置在氮化物半导体的晶体表面上的氮化硅（SiN）膜，该SiN膜具有等于或小于15％的氢含量。

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