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1. 发明申请

US20100237418A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237418A1
公开(公告)日：2010-09-23
申请号：US12793237
申请日：2010-06-03
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1285 , H01L27/1288 , H01L27/13 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78624
摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.
摘要翻译：本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。因此，可以精细地控制薄膜晶体管的性质。

2. 发明申请

US20120032236A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120032236A1
公开(公告)日：2012-02-09
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

3. 发明申请

US20090079000A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090079000A1
公开(公告)日：2009-03-26
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/08
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

4. 发明申请

US20080179675A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080179675A1
公开(公告)日：2008-07-31
申请号：US12015362
申请日：2008-01-16
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78618 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.
摘要翻译：具有改善其操作特性和可靠性的新颖结构的半导体器件及其制造方法。一种岛状半导体层，设置在衬底上，包括设置在一对杂质区之间的沟道形成区; 设置成与半导体层的侧表面接触的第一绝缘层; 栅电极，设置在所述沟道形成区上方以穿过所述半导体层; 并且包括设置在沟道形成区域和栅电极之间的第二绝缘层。半导体层被局部变薄，沟道形成区域设置在减薄区域中，并且第二绝缘层至少在与栅电极重叠的区域中覆盖设置在半导体层的侧表面上的第一绝缘层。

5. 发明申请

US20090078970A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090078970A1
公开(公告)日：2009-03-26
申请号：US12209696
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2924/00011 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/80001
摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
摘要翻译：示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

6. 发明申请

US20120214276A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120214276A1
公开(公告)日：2012-08-23
申请号：US13455425
申请日：2012-04-25
申请人： Yoshiaki OIKAWA , Hotaka MARUYAMA , Hiromichi GODO , Daisuke KAWAE , Shunpei YAMAZAKI
发明人： Yoshiaki OIKAWA , Hotaka MARUYAMA , Hiromichi GODO , Daisuke KAWAE , Shunpei YAMAZAKI
IPC分类号： H01L21/363
CPC分类号： H01L27/1225 , G02F1/1368 , G02F2201/121 , G02F2201/123 , H01L21/02565 , H01L21/02631 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L27/3248 , H01L27/3262 , H01L29/24 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
摘要翻译：本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏电极之间形成源极区或漏极区层和包含SiOX的In-Sn-O系氧化物半导体层。使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

7. 发明申请

US20100219410A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100219410A1
公开(公告)日：2010-09-02
申请号：US12706737
申请日：2010-02-17
申请人： Hiromichi GODO , Kengo AKIMOTO , Shunpei YAMAZAKI
发明人： Hiromichi GODO , Kengo AKIMOTO , Shunpei YAMAZAKI
IPC分类号： H01L29/786 , H01L29/22 , H01L21/44 , H01L21/34
CPC分类号： H01L29/78693 , H01L21/02554 , H01L21/02565 , H01L21/02573 , H01L21/02631 , H01L29/24 , H01L29/66742 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
摘要翻译：目的是为了减小阈值电压的变化，以稳定每个使用氧化物半导体层的薄膜晶体管的电特性。目的是减少关断电流。使用氧化物半导体层的薄膜晶体管通过在氧化物半导体层上层叠含有绝缘氧化物的氧化物半导体层而形成，使得氧化物半导体层和源极和漏极电极层彼此接触，氧化物半导体层包含绝缘体介于其间的氧化物; 从而可以减小薄膜晶体管的阈值电压的变化，从而能够稳定电特性。此外，可以减少截止电流。

8. 发明申请

US20090218576A1 THIN-FILM TRANSISTOR AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US20090218576A1
公开(公告)日：2009-09-03
申请号：US12390144
申请日：2009-02-20
申请人： Koji DAIRIKI , Hidekazu MIYAIRI , Yoshiyuki KUROKAWA , Shunpei YAMAZAKI , Hiromichi GODO , Daisuke KAWAE , Satoshi KOBAYASHI
发明人： Koji DAIRIKI , Hidekazu MIYAIRI , Yoshiyuki KUROKAWA , Shunpei YAMAZAKI , Hiromichi GODO , Daisuke KAWAE , Satoshi KOBAYASHI
IPC分类号： H01L33/00 , H01L29/786
CPC分类号： H01L27/1214 , H01L27/1288 , H01L29/04 , H01L29/458 , H01L29/4908 , H01L29/66765
摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.
摘要翻译：薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅极电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上间隔开; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

9. 发明申请

US20120061662A1 SEMICONDUCTOR DEVICE, POWER DIODE, AND RECTIFIER 有权
标题翻译：半导体器件，功率二极管和整流器
公开(公告)号：US20120061662A1
公开(公告)日：2012-03-15
申请号：US13220992
申请日：2011-08-30
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Satoshi KOBAYASHI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Satoshi KOBAYASHI
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L29/24 , H01L29/42356 , H01L29/78648
摘要： An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
摘要翻译：本发明的目的是提供具有诸如高耐受电压，低反向饱和电流和高导通电流等电特性的半导体器件。特别地，目的是提供一种包括非线性元件的功率二极管和整流器。本发明的一个实施例是一种半导体器件，包括第一电极，覆盖第一电极的栅极绝缘层，与栅极绝缘层接触并与第一电极重叠的氧化物半导体层，覆盖端部的一对第二电极所述氧化物半导体层的绝缘层，覆盖所述一对第二电极和所述氧化物半导体层的绝缘层，以及与所述绝缘层和所述一对第二电极接触的第三电极。一对第二电极与氧化物半导体层的端面接触。

10. 发明申请

US20110215317A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110215317A1
公开(公告)日：2011-09-08
申请号：US13037545
申请日：2011-03-01
申请人： Shunpei YAMAZAKI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Hiromichi GODO
IPC分类号： H01L27/088 , H01L29/78 , H01L21/34 , H01L21/8254
CPC分类号： G06F15/7832 , H01L27/1225 , H01L29/1033 , H01L29/7869
摘要： Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
摘要翻译：公开了一种半导体器件，其包括绝缘层，源电极和漏电极，该绝缘层嵌入在绝缘层中，与绝缘层，源极和漏电极接触的氧化物半导体层，覆盖氧化物的栅极绝缘层半导体层和栅绝缘层上的栅电极。与氧化物半导体层接触的绝缘层的表面的上表面的均方根（RMS）粗糙度为1nm以下。绝缘层的上表面与源电极的上表面和漏电极的上表面之间的高度差异。高度差优选为5nm以上。这种结构有助于抑制半导体器件的缺陷并使其能够小型化。

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