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1. 发明申请

US20110299533A1 INTERNAL VIRTUAL NETWORK IDENTIFIER AND INTERNAL POLICY IDENTIFIER 审中-公开
标题翻译：内部虚拟网络标识符和内部策略标识符
公开(公告)号：US20110299533A1
公开(公告)日：2011-12-08
申请号：US13050102
申请日：2011-03-17
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , Mythilikanth Raman , Rajiv Krishnamurthy , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , Mythilikanth Raman , Rajiv Krishnamurthy , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/56
CPC分类号： H04L12/4604 , H04L12/4625
摘要： Systems and techniques for processing and forwarding packets are described. Some embodiments provide a system (e.g., a switch) which determines an internal virtual network identifier and/or an internal policy identifier for a packet based on a port on which the packet was received and/or one or more fields in the packet. The system can then process and forward the packet based on the internal virtual network identifier and/or internal policy identifier. In some embodiments, the system encapsulates the packet in a TRILL (Transparent Interconnection of Lots of Links) packet by adding a TRILL header to the packet. In some embodiments, the scope of an internal virtual network identifier and/or an internal policy identifier may not extend beyond a switch or a module within a switch.
摘要翻译：描述了处理和转发数据包的系统和技术。一些实施例提供了一种系统（例如交换机），其基于接收到分组的端口和/或分组中的一个或多个字段来确定分组的内部虚拟网络标识符和/或内部策略标识符。然后系统可以基于内部虚拟网络标识符和/或内部策略标识符处理和转发数据包。在一些实施例中，通过向分组添加TRILL报头，系统将分组封装在TRILL（多个链路的透明互连）分组中。在一些实施例中，内部虚拟网络标识符和/或内部策略标识符的范围可能不会超出交换机内的交换机或模块。

2. 发明申请

US20110299414A1 PRESERVING QUALITY OF SERVICE ACROSS TRILL NETWORKS 审中-公开
标题翻译：保持网络服务质量
公开(公告)号：US20110299414A1
公开(公告)日：2011-12-08
申请号：US13048817
申请日：2011-03-15
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/26
CPC分类号： H04L47/2491 , H04L12/4641 , H04L45/00 , H04L45/66
摘要： Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.
摘要翻译：描述用于处理和/或转发分组的系统和技术。入口交换机可以使用QoS映射机制来将从客户端接收的分组中的第一组服务质量（QoS）比特映射到第二组QoS比特，以用于多个链路（TRILL）分组的透明互连它封装了数据包。第一组QoS位可以与第二组QoS位不同。 TRILL分组可以基于第二组QoS比特在网络中被处理和/或转发。在出口交换机上，可以对TRILL数据包进行解封装，将原始QoS位（或不同于原始QoS位的QoS位）的原始数据包转发到客户的网络。以这种方式，本发明的一些实施例可以保持跨TRILL网络的QoS比特。

3. 发明授权

US10033650B2 Preserving quality of service across trill networks 有权
公开(公告)号：US10033650B2
公开(公告)日：2018-07-24
申请号：US13048817
申请日：2011-03-15
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/723 , H04L12/66 , H04J1/16 , H04L12/857 , H04L12/46 , H04L12/701 , H04L12/721
摘要： Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

4. 发明授权

US08446914B2 Method and system for link aggregation across multiple switches 有权
公开(公告)号：US08446914B2
公开(公告)日：2013-05-21
申请号：US13092864
申请日：2011-04-22
申请人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
发明人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
IPC分类号： H04L12/56
CPC分类号： H04L45/66 , H04L12/4625 , H04L12/4633 , H04L45/00 , H04L45/245 , H04L49/70 , Y02D50/30
摘要： One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

5. 发明申请

US20110299536A1 METHOD AND SYSTEM FOR LINK AGGREGATION ACROSS MULTIPLE SWITCHES 有权
标题翻译：用于多个开关连接聚合的方法和系统
公开(公告)号：US20110299536A1
公开(公告)日：2011-12-08
申请号：US13092864
申请日：2011-04-22
申请人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
发明人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
IPC分类号： H04L12/56
CPC分类号： H04L45/66 , H04L12/4625 , H04L12/4633 , H04L45/00 , H04L45/245 , H04L49/70 , Y02D50/30
摘要： One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.
摘要翻译：本发明的一个实施例提供一种开关。交换机包括转发机制和控制机制。在运行期间，转发机制基于它们的以太网报头转发帧。所述控制机构将所述交换机与单独的物理交换机一起操作为单个逻辑交换机，并向所述逻辑交换机分配虚拟交换机标识符，其中所述虚拟交换机标识符与链路聚合组相关联。

6. 发明申请

US20120110411A1 Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection 审中-公开
标题翻译：内容可寻址内存（CAM）奇偶校验和纠错码（ECC）保护
公开(公告)号：US20120110411A1
公开(公告)日：2012-05-03
申请号：US12916384
申请日：2010-10-29
申请人： Wing Cheung , Joseph Juh-En Cheng , John Michael Terry
发明人： Wing Cheung , Joseph Juh-En Cheng , John Michael Terry
IPC分类号： G11C29/52 , H03M13/29 , H03M13/05 , G11C15/00 , G06F11/10
CPC分类号： G06F11/1666 , G06F11/106 , G11C15/04 , G11C2029/0411 , H03M13/09
摘要： A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.
摘要翻译：一种包括内容寻址存储器（CAM）阵列和非CAM阵列的存储器系统。可以与CAM阵列共享字线的非CAM阵列存储与CAM阵列的每一行相关联的一个或多个错误检测位。在CAM阵列的空闲周期期间，状态机读取CAM阵列的条目和非CAM阵列的相应错误检测位。错误检测逻辑识别从CAM阵列读取的条目中的错误（使用检索到的错误检测位）。如果这些错误是可纠正的，则错误检测逻辑校正条目，并将修正的条目写回CAM阵列（更新的错误检测位组也写入非CAM阵列）。如果这些错误不可纠正，则会产生一个中断，这会导致从CAM阵列的卷影副本中检索出正确的数据。

7. 发明申请

US20130031077A1 Longest Prefix Match Scheme 有权
标题翻译：最长前缀匹配方案
公开(公告)号：US20130031077A1
公开(公告)日：2013-01-31
申请号：US13284829
申请日：2011-10-28
申请人： Jian Liu , Philip Lynn Leichty , How Tung Lim , John Michael Terry , Mahesh Srinivasa Maddury , Wing Cheung , Kung Ling Ko
发明人： Jian Liu , Philip Lynn Leichty , How Tung Lim , John Michael Terry , Mahesh Srinivasa Maddury , Wing Cheung , Kung Ling Ko
IPC分类号： G06F17/30
CPC分类号： G06F7/02 , H04L45/7457 , H04L45/748
摘要： A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.
摘要翻译： LPM搜索引擎包括多个精确匹配（EXM）引擎和中等大小的TCAM。每个EXM引擎使用前缀位图方案，允许EXM引擎涵盖多个连续的前缀长度。因此，代替覆盖每个EXM引擎的一个前缀长度L，例如，前缀位图方案使得每个EXM引擎能够覆盖具有前缀长度为L，L + 1，L + 2和L + 3的条目。因此，较少的EXM引擎潜在地未充分利用，这有效地减少了量化损失。当使用前缀位图方案时，每个EXM引擎提供具有确定的固定延迟的搜索结果。多个EXM引擎和中等大小的TCAM的结果被组合以提供单个搜索结果，代表最长的前缀匹配。在一个实施例中，LPM搜索引擎支持32位IPv4（或128位IPv6）搜索密钥，每个具有关联的15位3级VPN标识值。

8. 发明授权

US08880494B2 Longest prefix match scheme 有权
标题翻译：最长前缀匹配方案
公开(公告)号：US08880494B2
公开(公告)日：2014-11-04
申请号：US13284829
申请日：2011-10-28
申请人： Jian Liu , Philip Lynn Leichty , How Tung Lim , John Michael Terry , Mahesh Srinivasa Maddury , Wing Cheung , Kung Ling Ko
发明人： Jian Liu , Philip Lynn Leichty , How Tung Lim , John Michael Terry , Mahesh Srinivasa Maddury , Wing Cheung , Kung Ling Ko
IPC分类号： G06F17/30 , H04L12/743 , G06F7/02 , H04L12/745
CPC分类号： G06F7/02 , H04L45/7457 , H04L45/748
摘要： A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.
摘要翻译： LPM搜索引擎包括多个精确匹配（EXM）引擎和中等大小的TCAM。每个EXM引擎使用前缀位图方案，允许EXM引擎涵盖多个连续的前缀长度。因此，代替覆盖每个EXM引擎的一个前缀长度L，例如，前缀位图方案使每个EXM引擎能够覆盖具有前缀长度为L，L + 1，L + 2和L + 3的条目。因此，较少的EXM引擎潜在地未充分利用，这有效地减少了量化损失。当使用前缀位图方案时，每个EXM引擎提供具有确定的固定延迟的搜索结果。多个EXM引擎和中等大小的TCAM的结果被组合以提供单个搜索结果，代表最长的前缀匹配。在一个实施例中，LPM搜索引擎支持32位IPv4（或128位IPv6）搜索密钥，每个具有关联的15位3级VPN标识值。

9. 发明授权

US08792366B2 Network packet latency measurement 有权
标题翻译：网络分组延迟测量
公开(公告)号：US08792366B2
公开(公告)日：2014-07-29
申请号：US12916060
申请日：2010-10-29
申请人： John Michael Terry , Wing Cheung , Surya Prakash Varanasi
发明人： John Michael Terry , Wing Cheung , Surya Prakash Varanasi
IPC分类号： H04L12/26
CPC分类号： H04L43/0852 , H04L41/5009
摘要： A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.
摘要翻译：用于网络分组等待时间测量的解决方案包括在具有存储器的网络设备处存储指示网络设备的入口端何时接收到分组的第一时间值。解决方案还包括存储指示网络设备的出口何时接收到分组用于传输到另一网络设备的第二时间值。解决方案还包括存储第一时间值和第二时间值之间的差异。

10. 发明申请

US20120106365A1 NETWORK PACKET LATENCY MEASUREMENT 有权
标题翻译：网络分组延迟测量
公开(公告)号：US20120106365A1
公开(公告)日：2012-05-03
申请号：US12916060
申请日：2010-10-29
申请人： John Michael Terry , Wing Cheung , Surya Prakash Varanasi
发明人： John Michael Terry , Wing Cheung , Surya Prakash Varanasi
IPC分类号： H04L12/26
CPC分类号： H04L43/0852 , H04L41/5009
摘要： A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.
摘要翻译：用于网络分组等待时间测量的解决方案包括在具有存储器的网络设备处存储指示网络设备的入口端何时接收到分组的第一时间值。解决方案还包括存储指示网络设备的出口何时接收到分组用于传输到另一网络设备的第二时间值。解决方案还包括存储第一时间值和第二时间值之间的差异。

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