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1. 发明申请

US20110299533A1 INTERNAL VIRTUAL NETWORK IDENTIFIER AND INTERNAL POLICY IDENTIFIER 审中-公开
标题翻译：内部虚拟网络标识符和内部策略标识符
公开(公告)号：US20110299533A1
公开(公告)日：2011-12-08
申请号：US13050102
申请日：2011-03-17
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , Mythilikanth Raman , Rajiv Krishnamurthy , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , Mythilikanth Raman , Rajiv Krishnamurthy , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/56
CPC分类号： H04L12/4604 , H04L12/4625
摘要： Systems and techniques for processing and forwarding packets are described. Some embodiments provide a system (e.g., a switch) which determines an internal virtual network identifier and/or an internal policy identifier for a packet based on a port on which the packet was received and/or one or more fields in the packet. The system can then process and forward the packet based on the internal virtual network identifier and/or internal policy identifier. In some embodiments, the system encapsulates the packet in a TRILL (Transparent Interconnection of Lots of Links) packet by adding a TRILL header to the packet. In some embodiments, the scope of an internal virtual network identifier and/or an internal policy identifier may not extend beyond a switch or a module within a switch.
摘要翻译：描述了处理和转发数据包的系统和技术。一些实施例提供了一种系统（例如交换机），其基于接收到分组的端口和/或分组中的一个或多个字段来确定分组的内部虚拟网络标识符和/或内部策略标识符。然后系统可以基于内部虚拟网络标识符和/或内部策略标识符处理和转发数据包。在一些实施例中，通过向分组添加TRILL报头，系统将分组封装在TRILL（多个链路的透明互连）分组中。在一些实施例中，内部虚拟网络标识符和/或内部策略标识符的范围可能不会超出交换机内的交换机或模块。

2. 发明申请

US20110299414A1 PRESERVING QUALITY OF SERVICE ACROSS TRILL NETWORKS 审中-公开
标题翻译：保持网络服务质量
公开(公告)号：US20110299414A1
公开(公告)日：2011-12-08
申请号：US13048817
申请日：2011-03-15
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/26
CPC分类号： H04L47/2491 , H04L12/4641 , H04L45/00 , H04L45/66
摘要： Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.
摘要翻译：描述用于处理和/或转发分组的系统和技术。入口交换机可以使用QoS映射机制来将从客户端接收的分组中的第一组服务质量（QoS）比特映射到第二组QoS比特，以用于多个链路（TRILL）分组的透明互连它封装了数据包。第一组QoS位可以与第二组QoS位不同。 TRILL分组可以基于第二组QoS比特在网络中被处理和/或转发。在出口交换机上，可以对TRILL数据包进行解封装，将原始QoS位（或不同于原始QoS位的QoS位）的原始数据包转发到客户的网络。以这种方式，本发明的一些实施例可以保持跨TRILL网络的QoS比特。

3. 发明授权

US10033650B2 Preserving quality of service across trill networks 有权
公开(公告)号：US10033650B2
公开(公告)日：2018-07-24
申请号：US13048817
申请日：2011-03-15
申请人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
发明人： Shunjia Yu , Anoop Ghanwani , Phanidhar Koganti , John Michael Terry , Wing Cheung , Joseph Juh-En Cheng , Surya P. Varanasi
IPC分类号： H04L12/723 , H04L12/66 , H04J1/16 , H04L12/857 , H04L12/46 , H04L12/701 , H04L12/721
摘要： Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

4. 发明授权

US08446914B2 Method and system for link aggregation across multiple switches 有权
公开(公告)号：US08446914B2
公开(公告)日：2013-05-21
申请号：US13092864
申请日：2011-04-22
申请人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
发明人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
IPC分类号： H04L12/56
CPC分类号： H04L45/66 , H04L12/4625 , H04L12/4633 , H04L45/00 , H04L45/245 , H04L49/70 , Y02D50/30
摘要： One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

5. 发明申请

US20110299536A1 METHOD AND SYSTEM FOR LINK AGGREGATION ACROSS MULTIPLE SWITCHES 有权
标题翻译：用于多个开关连接聚合的方法和系统
公开(公告)号：US20110299536A1
公开(公告)日：2011-12-08
申请号：US13092864
申请日：2011-04-22
申请人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
发明人： Joseph Juh-En Cheng , Wing Cheung , John Michael Terry , Suresh Vobbilisetty , Surya P. Varanasi , Parviz Ghalambor
IPC分类号： H04L12/56
CPC分类号： H04L45/66 , H04L12/4625 , H04L12/4633 , H04L45/00 , H04L45/245 , H04L49/70 , Y02D50/30
摘要： One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.
摘要翻译：本发明的一个实施例提供一种开关。交换机包括转发机制和控制机制。在运行期间，转发机制基于它们的以太网报头转发帧。所述控制机构将所述交换机与单独的物理交换机一起操作为单个逻辑交换机，并向所述逻辑交换机分配虚拟交换机标识符，其中所述虚拟交换机标识符与链路聚合组相关联。

6. 发明申请

US20120110411A1 Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection 审中-公开
标题翻译：内容可寻址内存（CAM）奇偶校验和纠错码（ECC）保护
公开(公告)号：US20120110411A1
公开(公告)日：2012-05-03
申请号：US12916384
申请日：2010-10-29
申请人： Wing Cheung , Joseph Juh-En Cheng , John Michael Terry
发明人： Wing Cheung , Joseph Juh-En Cheng , John Michael Terry
IPC分类号： G11C29/52 , H03M13/29 , H03M13/05 , G11C15/00 , G06F11/10
CPC分类号： G06F11/1666 , G06F11/106 , G11C15/04 , G11C2029/0411 , H03M13/09
摘要： A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.
摘要翻译：一种包括内容寻址存储器（CAM）阵列和非CAM阵列的存储器系统。可以与CAM阵列共享字线的非CAM阵列存储与CAM阵列的每一行相关联的一个或多个错误检测位。在CAM阵列的空闲周期期间，状态机读取CAM阵列的条目和非CAM阵列的相应错误检测位。错误检测逻辑识别从CAM阵列读取的条目中的错误（使用检索到的错误检测位）。如果这些错误是可纠正的，则错误检测逻辑校正条目，并将修正的条目写回CAM阵列（更新的错误检测位组也写入非CAM阵列）。如果这些错误不可纠正，则会产生一个中断，这会导致从CAM阵列的卷影副本中检索出正确的数据。

7. 发明授权

US08737418B2 Queue speed-up by using multiple linked lists 有权
标题翻译：通过使用多个链接列表来加速队列
公开(公告)号：US08737418B2
公开(公告)日：2014-05-27
申请号：US13032445
申请日：2011-02-22
申请人： Joseph Juh-En Cheng , Jian Liu
发明人： Joseph Juh-En Cheng , Jian Liu
IPC分类号： H04L12/54 , H04L12/56
CPC分类号： H04L47/6295 , H04L47/6225 , H04L49/9015 , H04L49/9047 , Y02D30/32
摘要： One embodiment of the present invention provides a switch that includes a transmission mechanism configured to transmit frames stored in a queue, and a queue management mechanism configured to store frames associated with the queue in a number of sub-queues which allow frames in different sub-queues to be retrieved independently, thereby facilitating parallel processing of the frames stored in the sub-queues.
摘要翻译：本发明的一个实施例提供了一种交换机，其包括被配置为发送存储在队列中的帧的传输机制，以及队列管理机制，被配置为在多个子队列中存储与队列相关联的帧，所述子队允许不同子帧中的帧，要独立检索的队列，从而便于并行处理存储在子队列中的帧。

8. 发明申请

US20120163396A1 QUEUE SPEED-UP BY USING MULTIPLE LINKED LISTS 有权
标题翻译：通过使用多个链接列表来加快队列速度
公开(公告)号：US20120163396A1
公开(公告)日：2012-06-28
申请号：US13032445
申请日：2011-02-22
申请人： Joseph Juh-En Cheng , Jian Liu
发明人： Joseph Juh-En Cheng , Jian Liu
IPC分类号： H04L12/56
CPC分类号： H04L47/6295 , H04L47/6225 , H04L49/9015 , H04L49/9047 , Y02D30/32
摘要： One embodiment of the present invention provides a switch that includes a transmission mechanism configured to transmit frames stored in a queue, and a queue management mechanism configured to store frames associated with the queue in a number of sub-queues which allow frames in different sub-queues to be retrieved independently, thereby facilitating parallel processing of the frames stored in the sub-queues.
摘要翻译：本发明的一个实施例提供了一种交换机，其包括被配置为发送存储在队列中的帧的传输机制，以及队列管理机制，被配置为在多个子队列中存储与队列相关联的帧，所述子队允许不同子帧中的帧，要独立检索的队列，从而便于并行处理存储在子队列中的帧。

9. 发明授权

US08625427B1 Multi-path switching with edge-to-edge flow control 有权
标题翻译：具有边缘到边缘流量控制的多路径切换
公开(公告)号：US08625427B1
公开(公告)日：2014-01-07
申请号：US12553689
申请日：2009-09-03
申请人： John M. Terry , Joseph Juh-En Cheng , Jan Bialkowski
发明人： John M. Terry , Joseph Juh-En Cheng , Jan Bialkowski
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
摘要： One embodiment of the present invention provides a system that facilitates flow control of multi-path-switched data frames. During operation the system transmits from an ingress edge device data frames destined to an egress edge device across different switched paths based on queue status of a core switching device and queue status of the egress edge device. The egress edge device is separate from the core switching device.
摘要翻译：本发明的一个实施例提供一种便于多路径交换数据帧的流控制的系统。在运行过程中，系统根据核心交换设备的队列状态和出口边缘设备的队列状态，从入口边缘设备发往目的地为出口边缘设备的数据帧跨越不同的交换路径。出口边缘设备与核心交换设备分离。

10. 发明授权

US08645609B2 Two-port memory implemented with single-port memory blocks 有权
标题翻译：使用单端口内存块实现双端口内存
公开(公告)号：US08645609B2
公开(公告)日：2014-02-04
申请号：US13035841
申请日：2011-02-25
申请人： Kung-Ling Ko , Tony Sonthe Nguyen , Joseph Juh-En Cheng , Tuan Van Quach
发明人： Kung-Ling Ko , Tony Sonthe Nguyen , Joseph Juh-En Cheng , Tuan Van Quach
IPC分类号： G06F12/00
CPC分类号： G11C7/1075
摘要： A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.
摘要翻译：具有读取端口，写入端口和多个相同的单端口RAM存储体的双端口存储器。其中一个单端口RAM存储体的容量用于解决对同一个单端口RAM存储体的同时读和写访问之间的冲突。读取映射存储器存储将逻辑存储体和备用存储体映射到单端口RAM存储体以用于读取访问的实例信息。类似地，写映射存储器存储将逻辑存储体和备用存储体映射到单端口RAM存储体以进行写访问的写实例信息。如果同时读写访问未映射到同一个单端口RAM存储区，则同时执行读写操作。然而，如果存在冲突，则写入访问被重新映射到由写入实例信息标识的备用库，从而允许同时读取和写入。读取和写入映射存储器都被更新以反映任何重新映射。

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