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1. 发明授权

US08198549B2 Multi-layer printed wiring board 失效
标题翻译：多层印刷线路板
公开(公告)号：US08198549B2
公开(公告)日：2012-06-12
申请号：US12004020
申请日：2007-12-20
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号： H05K1/11
CPC分类号： H05K1/112 , H05K1/0237 , H05K1/0298 , H05K2201/09227 , H05K2201/09236 , H05K2201/09518 , H05K2201/09627 , H05K2201/10159 , H05K2201/10734
摘要： A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.
摘要翻译：一种用于安装存储器的多层印刷电路板，包括：布置布线的层叠布线层; 以及电连接至少两个所述布线层的多个层间连接部件。多个层间连接部件中的至少一个是盲通孔。

2. 发明申请

US20100312925A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312925A1
公开(公告)日：2010-12-09
申请号：US12801327
申请日：2010-06-03
申请人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G06F13/00 , G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1066 , G11C7/1093 , G11C11/4076 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括沿着模块衬底的长边提供的多个数据连接器，多个存储器芯片和安装在模块衬底上的多个数据寄存器缓冲器，连接数据连接器和数据寄存器缓冲器的数据线以及连接数据寄存器缓冲器和存储器芯片的数据线。每个数据寄存器缓冲器和多个数据连接器以及对应于数据寄存器缓冲器的多个存储器芯片沿着模块基板的短边方向并排布置。根据本发明，由于数据线的每行长度大大缩短，所以可以实现相当高的数据传送速度。

3. 发明授权

US09368185B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09368185B2
公开(公告)日：2016-06-14
申请号：US14508744
申请日：2014-10-07
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号： G11C16/26 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/40603 , G11C16/26
摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
摘要翻译：半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

4. 发明申请

US20150098289A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150098289A1
公开(公告)日：2015-04-09
申请号：US14508744
申请日：2014-10-07
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/40603 , G11C16/26
摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
摘要翻译：半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

5. 发明授权

US08422263B2 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US08422263B2
公开(公告)日：2013-04-16
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

6. 发明授权

US07440289B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US07440289B2
公开(公告)日：2008-10-21
申请号：US11987080
申请日：2007-11-27
申请人： Toshio Sugano , Shunichi Saito , Atsushi Hiraishi
发明人： Toshio Sugano , Shunichi Saito , Atsushi Hiraishi
IPC分类号： H05K7/00
CPC分类号： H05K1/181 , G11C5/00 , H05K1/0298 , H05K2201/09254 , H05K2201/09627 , H05K2201/10159 , H05K2201/10545 , Y02P70/611
摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.
摘要翻译：存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器在与存储芯片MC3相对的位置经由模块基板。连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部的布线长度足够短。

7. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

8. 发明申请

US20080123303A1 Memory module 有权
标题翻译：内存模块
公开(公告)号：US20080123303A1
公开(公告)日：2008-05-29
申请号：US11987080
申请日：2007-11-27
申请人： Toshio Sugano , Shunichi Saito , Atsushi Hiraishi
发明人： Toshio Sugano , Shunichi Saito , Atsushi Hiraishi
IPC分类号： H05K7/00
CPC分类号： H05K1/181 , G11C5/00 , H05K1/0298 , H05K2201/09254 , H05K2201/09627 , H05K2201/10159 , H05K2201/10545 , Y02P70/611
摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.
摘要翻译：存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器在与存储芯片MC3相对的位置经由模块基板。连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部分的布线长度足够短。

9. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

10. 发明申请

US20080164058A1 Multi-layer printed wiring board 失效
标题翻译：多层印刷线路板
公开(公告)号：US20080164058A1
公开(公告)日：2008-07-10
申请号：US12004020
申请日：2007-12-20
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号： H05K1/11
CPC分类号： H05K1/112 , H05K1/0237 , H05K1/0298 , H05K2201/09227 , H05K2201/09236 , H05K2201/09518 , H05K2201/09627 , H05K2201/10159 , H05K2201/10734
摘要： A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.
摘要翻译：一种用于安装存储器的多层印刷电路板，包括：布置布线的层叠布线层; 以及电连接至少两个所述布线层的多个层间连接部件。多个层间连接部件中的至少一个是盲通孔。

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