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1. 发明授权

US07849235B2 DMA controller, node, data transfer control method and storage medium 有权
标题翻译： DMA控制器，节点，数据传输控制方法和存储介质
公开(公告)号：US07849235B2
公开(公告)日：2010-12-07
申请号：US11905373
申请日：2007-09-28
申请人： Shunichi Ihara , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Shunichi Ihara , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.
摘要翻译：响应于来自节点10的中央处理单元（CPU）11（即固件）的请求，直接存储器访问（DMA）控制器14的传送控制单元14a将消息和数据传送到另一个自由裁量节点3 串行总线1的方式，开关2等。在这种情况下，固件将要发送的数据，消息及其描述符存储在存储器12中。在请求发送消息的情况下，描述符包含指示“是否需要等待用于来自数据发送目的地的响应“。如果标志设置为ON，则传送控制单元14a立即通知固件仿真完成，而不是等待来自发送目的地节点3的完成响应。

2. 发明申请

US20080104341A1 DMA controller, node, data transfer control method and storage medium 有权
标题翻译： DMA控制器，节点，数据传输控制方法和存储介质
公开(公告)号：US20080104341A1
公开(公告)日：2008-05-01
申请号：US11905373
申请日：2007-09-28
申请人： Shunichi Ihara , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Shunichi Ihara , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.
摘要翻译：响应于来自节点10的中央处理单元（CPU）11（即固件）的请求，直接存储器访问（DMA）控制器14的传送控制单元14a将消息和数据发送到另一个可选节点3 通过串行总线1，开关2等。在这种情况下，固件将要发送的数据，消息及其描述符存储在存储器12中。在请求发送消息的情况下，描述符包含指示“是否需要等待来自数据发送目的地的响应”的标志。如果标志设置为ON，则传送控制单元14a立即通知固件仿真完成，而不是等待来自发送目的地节点3的完成响应。

3. 发明授权

US07624324B2 File control system and file control device 有权
标题翻译：文件控制系统和文件控制装置
公开(公告)号：US07624324B2
公开(公告)日：2009-11-24
申请号：US11237655
申请日：2005-09-29
申请人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.
摘要翻译：提供执行DMA（直接存储器访问）传送的文件控制系统。文件控制系统包括文件控制装置，并且每个文件控制装置设置在主计算机和外部存储装置之间。文件控制装置中的第一文件控制装置检查从存储器读取的数据中的错误，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，改变至少一部分当检测到错误时的数据，并且将改变或不改变的数据的DMA传送执行到传送目的地的第二文件控制装置。

4. 发明申请

US20070073960A1 PCI-Express communications system 有权
标题翻译： PCI-Express通信系统
公开(公告)号：US20070073960A1
公开(公告)日：2007-03-29
申请号：US11604361
申请日：2006-11-27
申请人： Yuichi Ogawa , Hiroshi Ishizawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuichi Ogawa , Hiroshi Ishizawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译：为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点。此外，确认在一系列分组传送中分组是否以正确的顺序传送。为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。

5. 发明申请

US20060190772A1 File control system and file control device 有权
标题翻译：文件控制系统和文件控制装置
公开(公告)号：US20060190772A1
公开(公告)日：2006-08-24
申请号：US11237655
申请日：2005-09-29
申请人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices, checks the consistency between the data read from a memory and the first error detection code given in advance to the data, changes the error detection code added to the read data from the first error detection code to a second error detection code, when the inconsistency is detected by the check, changes at least a part of the data comprising the second error detection code and the data associated with the second error detection code, and executes DMA-transfer of the data which is changed or is not changed to a second file control device of the transfer destination.
摘要翻译：本发明的文件控制系统是执行DMA传输的文件控制系统，包括多个文件控制装置，每个文件控制装置设置在主计算机和外部存储装置之间，多个文件中的第一文件控制装置控制装置检查从存储器读取的数据与预先给出的数据之间的第一错误检测码的一致性，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，当通过检查检测到不一致，改变包括第二错误检测码的数据的至少一部分和与第二错误检测码相关联的数据，并且执行被改变或不被改变的数据的DMA传送传送目的地的第二文件控制装置。

6. 发明授权

US07765357B2 PCI-express communications system 有权
标题翻译： PCI-express通信系统
公开(公告)号：US07765357B2
公开(公告)日：2010-07-27
申请号：US11604361
申请日：2006-11-27
申请人： Yuichi Ogawa , Hiroshi Ishizawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuichi Ogawa , Hiroshi Ishizawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F13/00 , G06F13/36 , G06F15/173
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译：为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点。此外，确认在一系列分组传送中分组是否以正确的顺序传送。为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。

7. 发明授权

US07461194B2 Apparatus for interconnecting a plurality of process nodes by serial bus 有权
标题翻译：用于通过串行总线互连多个处理节点的装置
公开(公告)号：US07461194B2
公开(公告)日：2008-12-02
申请号：US11133335
申请日：2005-05-20
申请人： Shigeyoshi Ohara , Kazunori Masuyama
发明人： Shigeyoshi Ohara , Kazunori Masuyama
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/28
摘要： Before the link of each port of a switch provide with a plurality of ports for interconnecting a plurality of process nodes by a serial bus is established, it is checked whether each process node is mounted. Then, of the plurality of ports, a port to which one of mounted process nodes is connected is assigned as an upstream port and the other ports are assigned as downstream ports.
摘要翻译：在交换机每个端口的链路提供用于通过串行总线互连多个处理节点的多个端口之前，检查每个进程节点是否被安装。然后，在多个端口中，连接有安装的处理节点的端口被分配为上行端口，并且其他端口被分配为下行端口。

8. 发明申请

US20060200614A1 Computer system using serial connect bus, and method for interconnecting a plurality of CPU using serial connect bus 有权
公开(公告)号：US20060200614A1
公开(公告)日：2006-09-07
申请号：US11168440
申请日：2005-06-29
申请人： Shigeyoshi Ohara , Kazunori Masuyama
发明人： Shigeyoshi Ohara , Kazunori Masuyama
IPC分类号： G06F13/00
CPC分类号： G06F13/28
摘要： A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express switch. When a CPU unit, which is connected to the upstream port of a serial connect switch interconnecting the plurality of CPU units, is unable to operate, and the links between the CPU units and the switch cannot be established, a management controller in the switch unit is selected as a device of the upstream port.

9. 发明授权

US07380001B2 Fault containment and error handling in a partitioned system with shared resources 有权
标题翻译：具有共享资源的分区系统中的故障控制和错误处理
公开(公告)号：US07380001B2
公开(公告)日：2008-05-27
申请号：US10150618
申请日：2002-05-17
申请人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
发明人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
IPC分类号： G06F15/173 , G06F15/00 , G06F11/00
CPC分类号： H04L41/12 , H04L41/0654 , H04L43/0817
摘要： A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.
摘要翻译：在分区计算机系统中的域内的用于故障容纳和错误处理的系统和方法包括具有对资源定义表的读取和写入访问的系统管理器。系统管理器适用于在域内发生故障时停止系统，识别与故障域相关联的分配资源，识别非故障域，并退出非故障域的静默模式，从而在失败的域。系统管理员通过取消分配给故障域的资源来进一步处理故障域内的错误，以使资源变得可用于非故障域。

10. 发明授权

US07194517B2 System and method for low overhead message passing between domains in a partitioned server 失效
标题翻译：分区服务器中域之间低开销消息传递的系统和方法
公开(公告)号：US07194517B2
公开(公告)日：2007-03-20
申请号：US10154100
申请日：2002-05-21
申请人： Patrick N. Conway , Jeremy J. Farrell , Kazunori Masuyama , Takeshi Shimizu , Sudheer Miryala
发明人： Patrick N. Conway , Jeremy J. Farrell , Kazunori Masuyama , Takeshi Shimizu , Sudheer Miryala
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： H04L67/2852 , H04L69/329
摘要： A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.
摘要翻译：一种用于在多节点计算机系统中具有低开销的域之间传递消息的系统和方法。发送域中的CPU节点使用存储器映射的输入/输出窗口向接收域中的存储器节点发出请求。这导致消息被发送到接收域的相干空间。所有消息都是高速缓存行大小。在将高速缓存行写入接收域的相干地址空间之前，每个高速缓存行的循环计数器字段的一小部分被重写。按摩驱动程序轮询处理器高速缓存中的高速缓存行的循环计数字段，以确定下一个消息何时被写入接收域的相干地址空间。这允许CPU检测最后接收的消息何时被写入接收域的相干地址空间，而不在CPU接口上生成事务。

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