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    • 2. 发明申请
    • SIGNAL PROCESSING APPARATUS
    • 信号处理装置
    • US20090207775A1
    • 2009-08-20
    • US12438996
    • 2007-11-29
    • Shuji MiyasakaMichihiro Matsumoto
    • Shuji MiyasakaMichihiro Matsumoto
    • H04H20/71H04L12/56G10L19/00
    • G10L19/167G10L21/038G11B2020/00028H04Q11/0428
    • When a coded signal having a layer structure is generated, insertion of header information in a sub-layer in each frame increases the bit rate. In contrast, when the header information is only inserted at regular intervals, a reproducer sometimes cannot obtain information necessary in a reproduction start point.The signal processing apparatus inserts the header information in a frame to probably be the reproduction start point by including: the first (100) and the second (101) coding units that code an input signal per frame; the first header inserting unit (103) that inserts the SBR header indicating management information of the coded signal represented by a sequence of frames, in each frame at a regular interval within the coded signal; the control unit (105) that determines a frame in which the SBR header is inserted, independent of the frames in which the first header inserting unit inserts the SBR header; and the second header inserting unit (104) that singly inserts the SBR header in the frame determined by the control unit.
    • 当产生具有层结构的编码信号时,标题信息在每个帧中的子层中的插入增加了位速率。 相反,当标题信息仅以规则的间隔插入时,再现器有时不能获得再现开始点所需的信息。 信号处理装置通过包括:对每帧输入信号进行编码的第一(100)和第二(101)个编码单元,将标题信息插入到可能是再现开始点的帧中; 第一标题插入单元,以编码信号内的规则间隔插入指示由帧序列表示的编码信号的管理信息的SBR标题; 控制单元(105),其独立于第一报头插入单元插入SBR报头的帧,确定其中插入SBR报头的帧; 以及在由控制单元确定的帧中单独地插入SBR头部的第二头插入单元(104)。
    • 10. 发明申请
    • Variable length decoding device and variable length decoding method and reproducing system
    • 可变长度解码装置和可变长度解码方法和再现系统
    • US20050168362A1
    • 2005-08-04
    • US11050880
    • 2005-01-27
    • Yoshihiro KogaMasakazu FujimotoMichihiro Matsumoto
    • Yoshihiro KogaMasakazu FujimotoMichihiro Matsumoto
    • G06F12/04H03M7/40H04N19/00H04N19/423H04N19/44H04N19/91
    • H03M7/40
    • A variable length decoding device comprising: a memory for laying out data which is identical to data memorized on a lower-bit side at an optional address on an upper-bit side at an address subsequent to the optional address and memorizing the layed-out data; a buffer register having a bit width at least equal to a bit width of the memory for storing data loaded from the memory; and an address register for storing a value of an address at which the memory is accessed (address value) on an upper-bit side and storing number of data which was referred to in the buffer register on a lower-bit side, characterized in that a data shift operation using the number of the data which was referred to and number of data which is currently referred to is executed to the buffer register so that data to be presently referred to is extracted from the buffer register for the variable length decoding, the number of the data which was referred to on the lower-bit side of the address register is renewed by adding thereto the number of the data which has been currently referred to in response to the extraction of the data from the buffer register, the address value to be stored on the upper-bit side of the address register is maintained when the renewed number of the data which was referred to on the lower-bit side of the address register is not carried up, and the carry-up is used to renew the address value to be a next address value when the renewed number of the data is carried up.
    • 一种可变长度解码装置,包括:存储器,用于布置与位于所述可选地址之后的地址处的高位位置的可选地址存储在低位侧的数据相同的数据,并存储所述布局数据 ; 缓冲寄存器,其位宽至少等于用于存储从存储器加载的数据的存储器的位宽度; 以及地址寄存器,用于存储高位访问存储器的地址的值(地址值),并存储在低位侧的缓冲寄存器中所参考的数据的数量,其特征在于: 使用所参考的数据的数量和当前参考的数据的数量的数据移位操作被执行到缓冲寄存器,使得从缓冲寄存器中提取当前参考的数据用于可变长度解码, 在地址寄存器的低位侧所引用的数据的数量是通过将来自缓冲寄存器的数据的提取响应于当前参考的数据的数量相加来更新的,地址值 当在地址寄存器的低位侧所参考的更新的数据的数量不被携带时,保存在地址寄存器的高位位侧的存储器,并且使用进位 当更新的数据数据被携带时,将地址值更新为下一个地址值。