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1. 发明授权

US4615104A Method of forming isolation regions containing conductive patterns therein 失效
公开(公告)号：US4615104A
公开(公告)日：1986-10-07
申请号：US738404
申请日：1985-05-28
申请人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
发明人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76 , H01L21/88
CPC分类号： H01L21/763 , H01L21/76229 , Y10S148/02 , Y10S148/05 , Y10S148/085
摘要： A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

2. 发明授权

US4615103A Method of forming isolation regions containing conductive patterns therein 失效
标题翻译：形成其中包含导电图案的隔离区域的方法
公开(公告)号：US4615103A
公开(公告)日：1986-10-07
申请号：US737922
申请日：1985-05-28
申请人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
发明人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76 , H01L21/88
CPC分类号： H01L21/763 , H01L21/76229 , Y10S148/02 , Y10S148/05 , Y10S148/085
摘要： A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

3. 发明授权

US4532701A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4532701A
公开(公告)日：1985-08-06
申请号：US410083
申请日：1982-08-19
申请人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
发明人： Shuichi Kameyama , Satoshi Shinozaki , Hiroshi Iwai
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76229 , Y10S148/02 , Y10S148/05 , Y10S148/085
摘要： A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.
摘要翻译：一种制造半导体器件的方法，包括在半导体层中形成第一凹槽的步骤，用第一绝缘膜填充第一凹槽的步骤，选择性地蚀刻第一凹槽中的第一绝缘膜以形成具有小宽度的至少一个第二凹槽，以及用第二绝缘膜填充第二凹槽的步骤，以形成宽度大致与半导体层基本齐平的隔离层。

4. 发明授权

US07914325B2 Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them 失效
标题翻译：连接器，印刷电路板，连接它们的连接装置，以及使用它们的电子部件的测试方法
公开(公告)号：US07914325B2
公开(公告)日：2011-03-29
申请号：US12588822
申请日：2009-10-29
申请人： Masayuki Baba , Shuichi Kameyama
发明人： Masayuki Baba , Shuichi Kameyama
IPC分类号： H01R13/60 , H01R13/66
CPC分类号： H05K1/0268 , G01R1/0416 , G01R31/2815 , H01R12/7023 , H05K1/0219 , H05K3/301 , H05K2201/09063 , H05K2201/10598
摘要： The invention has an object of providing a connector for connecting between a printed circuit board and a test device, capable of easily attaching and detaching the connector at low cost. The connector includes at least one conducting pin 28 that is protruded from a connector body, and at least one fixing pin 30 that is extended substantially in parallel with the conducting pin. The fixing pin 30 is longer than the conducting pin 28.
摘要翻译：本发明的目的是提供一种用于连接印刷电路板和测试装置的连接器，其能够以低成本容易地连接和拆卸连接器。连接器包括从连接器本体突出的至少一个导电销28和至少一个基本上平行于导电销延伸的固定销30。固定销30比导电销28长。

5. 发明授权

US5436176A Method for fabricating a semiconductor device by high energy ion implantation while minimizing damage within the semiconductor substrate 失效
标题翻译：通过高能离子注入制造半导体器件的方法，同时使半导体衬底内的损伤最小化
公开(公告)号：US5436176A
公开(公告)日：1995-07-25
申请号：US821647
申请日：1992-01-16
申请人： Norisato Shimizu , Bunji Mizuno , Shuichi Kameyama
发明人： Norisato Shimizu , Bunji Mizuno , Shuichi Kameyama
IPC分类号： H01L21/265 , H01L21/322 , H01L21/74 , H01L21/8238 , H01L27/092 , H01L21/22
CPC分类号： H01L21/2652 , H01L21/74
摘要： A semiconductor device having superior electrical characteristics is fabricated. 50 nm of the surface of a CZ (100) silicon substrate is oxidized to form an oxidized film. Afterwards a first ion implantation of boron ions is conducted to this silicon substrate amounting to 7.times.10.sup.13 cm.sup.-2 with acceleration energy of 1.5 MeV. Next, a first annealing in nitrogen ambient at 1050.degree. C. for 40 minutes is conducted. Through this ion implantation process a damaged layer and a dopant layer are formed within the silicon substrate. Boron ions are implanted as a second ion implantation, with a dosage of 7.times.10.sup.13 cm.sup.-2, followed by a second implanted annealing in nitrogen ambient at 1050.degree. C. for 40 minutes. Further, as a third ion implantation, boron ions are implanted with a dosage of 6.times.10.sup.13 cm.sup.-2 followed by a third annealing in nitrogen ambient at 1050.degree. C. for 40 minutes. In the dopant layer thus formed, through a plurality of repeated high energy ion implantation and subsequent annealing, in order to obtain the desired dopant concentration, density of secondary defect occurrences may be lowered.
摘要翻译：制造具有优异电特性的半导体器件。 CZ（100）硅衬底的表面的50nm被氧化以形成氧化膜。此后，以1.5MeV的加速能量对该硅衬底进行第一离子注入，达到7×10 13 cm -2。接下来，进行在1050℃，氮气环境中进行40分钟的第一次退火。通过该离子注入工艺，在硅衬底内形成损伤层和掺杂剂层。硼离子作为第二离子注入植入，剂量为7×10 13 cm -2，随后在氮环境中在1050℃下进行第二次注入退火40分钟。此外，作为第三离子注入，硼离子以6×10 13 cm -2的剂量注入，然后在氮环境中在1050℃下进行第三次退火40分钟。在如此形成的掺杂剂层中，通过多次重复的高能离子注入和随后的退火，为了获得所需的掺杂剂浓度，二次缺陷发生的密度可能降低。

6. 发明授权

US5270227A Method for fabrication of semiconductor device utilizing ion implantation to eliminate defects 失效
标题翻译：利用离子注入制造半导体器件以消除缺陷的方法
公开(公告)号：US5270227A
公开(公告)日：1993-12-14
申请号：US858107
申请日：1992-03-26
申请人： Shuichi Kameyama , Genshu Fuse
发明人： Shuichi Kameyama , Genshu Fuse
IPC分类号： H01L21/265 , H01L21/28 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/732 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66272 , H01L21/26586 , H01L21/8249 , H01L29/6659 , H01L29/78 , Y10S148/01
摘要： An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as "voids 21" which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.

7. 发明申请

US20080316725A1 Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them 失效
标题翻译：连接器，印刷电路板，连接它们的连接装置，以及使用它们的电子部件的测试方法
公开(公告)号：US20080316725A1
公开(公告)日：2008-12-25
申请号：US12222553
申请日：2008-08-12
申请人： Masayuki Baba , Shuichi Kameyama
发明人： Masayuki Baba , Shuichi Kameyama
IPC分类号： H05K7/06
CPC分类号： H05K1/0268 , G01R1/0416 , G01R31/2815 , H01R12/7023 , H05K1/0219 , H05K3/301 , H05K2201/09063 , H05K2201/10598
摘要： The invention has an object of providing a connector for connecting between a printed circuit board and a test device, capable of easily attaching and detaching the connector at low cost. The connector includes at least one conducting pin 28 that is protruded from a connector body, and at least one fixing pin 30 that is extended substantially in parallel with the conducting pin. The fixing pin 30 is longer than the conducting pin 28.
摘要翻译：本发明的目的是提供一种用于连接印刷电路板和测试装置的连接器，其能够以低成本容易地连接和拆卸连接器。连接器包括从连接器本体突出的至少一个导电销28和至少一个基本上平行于导电销延伸的固定销30。固定销30比导电销28长。

8. 发明授权

US07425151B2 Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them 失效
公开(公告)号：US07425151B2
公开(公告)日：2008-09-16
申请号：US11657463
申请日：2007-01-25
申请人： Masayuki Baba , Shuichi Kameyama
发明人： Masayuki Baba , Shuichi Kameyama
IPC分类号： H01R13/60
CPC分类号： H05K1/0268 , G01R1/0416 , G01R31/2815 , H01R12/7023 , H05K1/0219 , H05K3/301 , H05K2201/09063 , H05K2201/10598
摘要： The invention has an object of providing a connector for connecting between a printed circuit board and a test device, capable of easily attaching and detaching the connector at low cost. The connector includes at least one conducting pin 28 that is protruded from a connector body, and at least one fixing pin 30 that is extended substantially in parallel with the conducting pin. The fixing pin 30 is longer than the conducting pin 28.

9. 发明授权

US5202277A Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5202277A
公开(公告)日：1993-04-13
申请号：US918933
申请日：1992-07-22
申请人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
发明人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28114
摘要： A method of fabricating a semiconductor device having gate-drain overlap MOSFETs in which side surfaces of upper portions of gate lines are anisotropically etched using a buffer film as an etch stop is disclosed. An insulating film as a gate insulator is formed on a semiconductor layer of a first conductivity type. A first conductive film is formed on the gate insulator. A buffer film having openings in gate line regions is formed on the first conductive film. A second conductive film is formed on the buffer film. The second conductive film is patterned into wiring shape to form upper portions of gate lines covering the openings of the buffer film. Ions of a second conductivity type are implanted into the semiconductor layer using the upper portions of the gate lines as an implant mask to form sources and drains in the semiconductor layer. Sidewall spacers are formed on the sides of the upper portions of the gate lines. The buffer film and the first conductive film are etched using the upper portions of the gate lines and the sidewall spacers as an etching mask to form under portions of the gate lines.
摘要翻译：公开了一种制造具有栅极 - 漏极重叠MOSFET的半导体器件的方法，其中栅极线的上部的侧表面使用缓冲膜作为蚀刻停止点进行各向异性蚀刻。作为栅极绝缘体的绝缘膜形成在第一导电类型的半导体层上。在栅极绝缘体上形成第一导电膜。在第一导电膜上形成在栅线区域具有开口的缓冲膜。在缓冲膜上形成第二导电膜。将第二导电膜图案化成布线形状，以形成覆盖缓冲膜的开口的栅极线的上部。使用栅极线的上部作为注入掩模将第二导电类型的离子注入到半导体层中，以在半导体层中形成源极和漏极。侧壁间隔件形成在栅极线的上部的侧面上。使用栅极线和侧壁间隔物的上部作为蚀刻掩模蚀刻缓冲膜和第一导电膜，以在栅极线的一部分形成。

10. 发明授权

US4445967A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4445967A
公开(公告)日：1984-05-01
申请号：US423092
申请日：1982-09-24
申请人： Shuichi Kameyama
发明人： Shuichi Kameyama
IPC分类号： H01L21/76 , H01L21/31 , H01L21/762 , H01L21/306 , B44C1/22 , C03C15/00 , H01L21/312
CPC分类号： H01L21/76232 , H01L21/76229
摘要： The invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a mask material pattern at least on a portion of a semiconductor layer which corresponds to a prospective element formation region; etching the semiconductor layer, using the mask material pattern, to form a first groove which is wide and shallow; burying a first isolating material in the first groove to a thickness substantially equal to the depth of the first groove; etching a portion of the first isolating material film which is located in the vicinity of the prospective element formation region to partially expose a bottom of the first groove, thereby forming a second groove which is narrower than said first groove, a position of the second groove being defined by the mask material pattern; forming a third groove which is deeper than said first and second grooves by etching a bottom of the second groove; and burying a second isolating material in the third groove.
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：至少在对应于预期元件形成区域的半导体层的一部分上形成掩模材料图案; 使用掩模材料图案蚀刻半导体层，以形成宽而浅的第一凹槽; 将第一槽中的第一隔离材料埋入基本上等于第一槽的深度的厚度; 蚀刻位于预期元件形成区域附近的第一隔离材料膜的一部分以部分地暴露第一槽的底部，从而形成比第一槽窄的第二槽，第二槽的位置由掩模材料图案限定; 通过蚀刻所述第二凹槽的底部形成比所述第一和第二凹槽更深的第三凹槽; 并在第三凹槽中埋设第二隔离材料。

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