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1. 发明授权

US06762439B1 Diode for power protection 有权
标题翻译：二极管用于电源保护
公开(公告)号：US06762439B1
公开(公告)日：2004-07-13
申请号：US09898386
申请日：2001-07-05
申请人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih , Ta-Lee Yu
发明人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih , Ta-Lee Yu
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.
摘要翻译：实现了新的静电放电保护装置。 p阱区位于半导体衬底中。 p阱区域中的n +区域连接到第一电压源。 p阱区域中的n阱区域与n +区域间隔开，使得在正常操作期间耗尽区域将在其间延伸。在正常操作期间，n阱区域中的p +区域连接到比第一电压源更大的值的第二电压源。在静电放电事件期间，电流通过n +区域传导到p +区域。

2. 发明申请

US20050176195A1 Decoupling capacitor 有权
公开(公告)号：US20050176195A1
公开(公告)日：2005-08-11
申请号：US11072014
申请日：2005-03-04
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01G4/228 , H01G4/35 , H01L21/8234 , H01L23/60 , H02H9/00
CPC分类号： H01L27/0251
摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

3. 发明授权

US06614078B2 Highly latchup-immune CMOS I/O structures 有权
公开(公告)号：US06614078B2
公开(公告)日：2003-09-02
申请号：US10147272
申请日：2002-05-16
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Ping-Lung Liao
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Ping-Lung Liao
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921
摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

4. 发明授权

US06420221B1 Method of manufacturing a highly latchup-immune CMOS I/O structure 有权
标题翻译：制造高度闭锁免疫CMOS I / O结构的方法
公开(公告)号：US06420221B1
公开(公告)日：2002-07-16
申请号：US09507646
申请日：2000-02-22
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-hung Chen , Ping-Lung Liao
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-hung Chen , Ping-Lung Liao
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L27/0921
摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.
摘要翻译：通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

5. 发明授权

US06323523B1 N-type structure for n-type pull-up and down I/O protection circuit 有权
标题翻译： N型结构用于n型上拉和下拉I / O保护电路
公开(公告)号：US06323523B1
公开(公告)日：2001-11-27
申请号：US09494682
申请日：2000-01-31
申请人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.
摘要翻译：公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区，上拉晶体管耦合到电源。下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。包括p +保护的下拉晶体管的所有源极区域接地。所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

6. 发明授权

US06277723B1 Plasma damage protection cell using floating N/P/N and P/N/P structure 有权
标题翻译：使用浮动N / P / N和P / N / P结构的等离子体损伤保护电池
公开(公告)号：US06277723B1
公开(公告)日：2001-08-21
申请号：US09418030
申请日：1999-10-14
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
IPC分类号： H01L2144
CPC分类号： H01L21/28123
摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
摘要翻译：公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

7. 发明授权

US6122201A Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM 有权
标题翻译：缩短正弦波通道擦除方法，以减少闪存EEPROM的氧化物俘获电荷产生速率
公开(公告)号：US6122201A
公开(公告)日：2000-09-19
申请号：US421516
申请日：1999-10-20
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.
摘要翻译：在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM擦除数据的方法，以便在延长编程和擦除周期之后，保持编程阈值电压和擦除阈值电压的适当分离。通过从闪存EEPROM单元的浮动栅极去除电荷，开始通道擦除闪存EEPROM单元的方法。通道擦除包括将相对较大的限幅正弦负电压脉冲施加到所述EEPROM单元的控制栅极，同时向第一扩散区域施加适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极，源极和第二扩散阱浮动。

8. 发明授权

US06614693B1 Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM 有权
标题翻译：组合擦除波形，以减少闪存EEPROM的氧化物捕获中心产生速率
公开(公告)号：US06614693B1
公开(公告)日：2003-09-02
申请号：US10100752
申请日：2002-03-19
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： G11C1604
CPC分类号： G11C16/3404 , G11C16/16
摘要： A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.
摘要翻译：从闪存EEPROM擦除数据的组合擦除方法消除了在快速EEPROM的隧道氧化物中捕获的电荷，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除快闪EEPROM单元的第一实施例方法是通过负栅极擦除开始，以从浮置栅极去除电荷，随后进行源擦除以进一步从浮置栅极去除电荷，最后再进行通道擦除以去除电荷。第二实施例开始于负栅极擦除，其具有电压的增量步进以从浮置栅极去除电荷。之后是源擦除来去除EEPROM单元的隧道氧化物。第三实施例开始于具有逐渐增加的步进电压以从浮动栅极去除电荷的源擦除。之后是通道擦除以去除EEPROM单元的隧穿氧化物。

9. 发明授权

US06541824B2 Modified source side inserted anti-type diffusion ESD protection device 有权
公开(公告)号：US06541824B2
公开(公告)日：2003-04-01
申请号：US09957275
申请日：2001-09-21
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Yi-Hsun Wu
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Yi-Hsun Wu
IPC分类号： H01L2362
CPC分类号： H01L27/0277 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.

10. 发明授权

US06362035B1 Channel stop ion implantation method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的通道停止离子注入方法
公开(公告)号：US06362035B1
公开(公告)日：2002-03-26
申请号：US09498741
申请日：2000-02-07
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Hsien-Chin Lin
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Hsien-Chin Lin
IPC分类号： H01L2144
CPC分类号： H01L21/823878 , H01L21/76237 , Y10S438/919
摘要： A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.
摘要翻译：描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。该方法在利用浅沟槽隔离的工艺中示出并且特别有效。

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