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1. 发明授权

US07433219B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US07433219B2
公开(公告)日：2008-10-07
申请号：US11341029
申请日：2006-01-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

2. 发明申请

US20060209583A1 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US20060209583A1
公开(公告)日：2006-09-21
申请号：US11341029
申请日：2006-01-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

3. 发明授权

US07813154B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US07813154B2
公开(公告)日：2010-10-12
申请号：US12199684
申请日：2008-08-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

4. 发明授权

US08023341B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US08023341B2
公开(公告)日：2011-09-20
申请号：US12903065
申请日：2010-10-12
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C7/10
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

5. 发明申请

US20080316787A1 METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中寻址和验证的方法和装置
公开(公告)号：US20080316787A1
公开(公告)日：2008-12-25
申请号：US12199684
申请日：2008-08-27
申请人： Shozo KAWABATA , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo KAWABATA , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00 , G11C8/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

6. 发明授权

US06977411B2 Semiconductor device comprising transistors having control gates and floating gate electrodes 有权
标题翻译：包括具有控制栅极和浮置栅电极的晶体管的半导体器件
公开(公告)号：US06977411B2
公开(公告)日：2005-12-20
申请号：US10738025
申请日：2003-12-18
申请人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
发明人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.
摘要翻译：半导体器件包括形成在半导体衬底10中的第一导电类型的第一阱14; 形成在第一阱14中的第二导电类型的第二阱16; 以及晶体管40，其包括由形成在第二阱16中的第一导电类型的杂质区域形成的控制栅极18，在其间形成有沟道区域25的第一杂质扩散层26和第二杂质扩散层33，以及浮置栅极电极20形成在沟道区域25和控制栅极18之间，栅极绝缘膜24在其间。控制栅极18被埋在半导体衬底10中，这使得不必在浮栅电极20上形成控制栅极18。因此，可以通过相同的制造工艺来形成存储晶体管和其它晶体管等。因此，制造工艺可以更少，并且半导体器件可以是便宜的。

7. 发明授权

US07415568B2 Method and apparatus for initialization control in a non-volatile memory device 有权
标题翻译：用于非易失性存储器件中的初始化控制的方法和装置
公开(公告)号：US07415568B2
公开(公告)日：2008-08-19
申请号：US11194111
申请日：2005-07-28
申请人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
发明人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
IPC分类号： G11C16/02
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/20 , G11C16/20 , G11C16/26 , G11C16/344
摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.
摘要翻译：当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12））。在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据外部读取访问请求到非冗余存储器区域。在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。此后，读出重写操作信息（S18）。因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

8. 发明授权

US07452771B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07452771B2
公开(公告)日：2008-11-18
申请号：US11248137
申请日：2005-10-13
申请人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
发明人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.
摘要翻译：半导体器件包括形成在半导体衬底10中的第一导电类型的第一阱14; 形成在第一阱14中的第二导电类型的第二阱16; 以及晶体管40，其包括由形成在第二阱16中的第一导电类型的杂质区域形成的控制栅极18，在其间形成有沟道区域25的第一杂质扩散层26和第二杂质扩散层33，以及浮置栅极电极20形成在沟道区域25和控制栅极18之间，栅极绝缘膜24在其间。控制栅极18被埋在半导体衬底10中，这使得不需要在浮栅电极20上形成控制栅极18。因此，可以通过相同的制造工艺来形成存储晶体管和其它晶体管等。因此，制造工艺可以更少，并且半导体器件可以是便宜的。

9. 发明申请

US20060046373A1 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20060046373A1
公开(公告)日：2006-03-02
申请号：US11248137
申请日：2005-10-13
申请人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
发明人： Masaki Ito , Masaya Katayama , Takaaki Furuyama , Shozo Kawabata
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.
摘要翻译：半导体器件包括形成在半导体衬底10中的第一导电类型的第一阱14; 形成在第一阱14中的第二导电类型的第二阱16; 以及晶体管40，其包括由形成在第二阱16中的第一导电类型的杂质区域形成的控制栅极18，在其间形成有沟道区域25的第一杂质扩散层26和第二杂质扩散层33，以及浮置栅极电极20形成在沟道区域25和控制栅极18之间，栅极绝缘膜24在其间。控制栅极18被埋在半导体衬底10中，这使得不需要在浮栅电极20上形成控制栅极18。因此，可以通过相同的制造工艺来形成存储晶体管和其它晶体管等。因此，制造工艺可以更少，并且半导体器件可以是便宜的。

10. 发明申请

US20060023500A1 Method and apparatus for initialization control in a non-volatile memory device 有权
标题翻译：用于非易失性存储器件中的初始化控制的方法和装置
公开(公告)号：US20060023500A1
公开(公告)日：2006-02-02
申请号：US11194111
申请日：2005-07-28
申请人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
发明人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/20 , G11C16/20 , G11C16/26 , G11C16/344
摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.
摘要翻译：当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12））。在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据外部读取访问请求到非冗余存储器区域。在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。此后，读出重写操作信息（S18）。因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

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