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1. 发明申请

US20110155904A1 Method and Apparatus for Pattern Position and Overlay Measurement 有权
标题翻译：图形位置和叠加测量的方法和装置
公开(公告)号：US20110155904A1
公开(公告)日：2011-06-30
申请号：US12648766
申请日：2009-12-29
申请人： Shoji HOTTA , Norio Hasegawa
发明人： Shoji HOTTA , Norio Hasegawa
IPC分类号： G01N23/00 , G01B15/00
CPC分类号： G03F7/70466 , G03F7/70633 , G06T7/60 , G06T2207/10061 , G06T2207/30148 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.
摘要翻译：使用成像装置图案的系统和方法来测量半导体制造工艺中的不同层之间的覆盖层，例如双重图案化工艺。通过扫描电子显微镜获得图案特征的图像。使用图像中的图案化层的图案特征的位置来确定图案化层的位置。基于所确定的图案位置，以向量形式确定每个图案形成层相对于其它图案特征或图案化层的相对位置。叠加误差是根据相对位置与设计或模拟参考值的比较来确定的。可以通过利用图案对称性以高精度和精度测量覆盖层。

2. 发明申请

US20050090120A1 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20050090120A1
公开(公告)日：2005-04-28
申请号：US10967277
申请日：2004-10-19
申请人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
发明人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
IPC分类号： G03C5/00 , G03F1/30 , G03F1/32 , G03F1/68 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/311 , H01L21/768
CPC分类号： H01L21/76808 , G03F1/30 , G03F1/32 , G03F1/50 , H01L21/31144
摘要： In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.
摘要翻译：在掩模的多个转印区域的每一个的质量区域中，通过打开半色调膜形成多个透光图案。在每个透光图案中设置移相器，使得在通过相邻光传输图案传输的光之间发生180°的相位反转。在多个转印区域的稀疏区域中，通过打开半色调膜形成单独的透光图案。在透光图案之间的形状和尺寸都相同，所述光透射图案在转印区域之间的中心周围的质量和稀疏区域中对称地设置。配置区域中的移相器被布置成使得其中一个传送区域中的每个移相器的相位与其它传送区域中的相应部件的相位相反。在曝光处理中，这些传送区域在相同的芯片区域中彼此重叠。

3. 发明授权

US07387867B2 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07387867B2
公开(公告)日：2008-06-17
申请号：US10967277
申请日：2004-10-19
申请人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
发明人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
IPC分类号： G03F7/00
CPC分类号： H01L21/76808 , G03F1/30 , G03F1/32 , G03F1/50 , H01L21/31144
摘要： In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.
摘要翻译：在掩模的多个转印区域的每一个的质量区域中，通过打开半色调膜形成多个透光图案。在每个透光图案中设置移相器，使得在通过相邻光传输图案传输的光之间发生180°的相位反转。在多个转印区域的稀疏区域中，通过打开半色调膜形成单独的透光图案。在透光图案之间的形状和尺寸都相同，所述光透射图案在转印区域之间的中心周围的质量和稀疏区域中对称地设置。配置区域中的移相器被布置成使得其中一个传送区域中的每个移相器的相位与其它传送区域中的相应部件的相位相反。在曝光处理中，这些传送区域在相同的芯片区域中彼此重叠。

4. 发明授权

US08148682B2 Method and apparatus for pattern position and overlay measurement 有权
标题翻译：图案位置和重叠测量的方法和装置
公开(公告)号：US08148682B2
公开(公告)日：2012-04-03
申请号：US12648766
申请日：2009-12-29
申请人： Shoji Hotta , Norio Hasegawa
发明人： Shoji Hotta , Norio Hasegawa
IPC分类号： G01N23/00
CPC分类号： G03F7/70466 , G03F7/70633 , G06T7/60 , G06T2207/10061 , G06T2207/30148 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.
摘要翻译：使用成像装置图案的系统和方法来测量半导体制造工艺中的不同层之间的覆盖层，例如双重图案化工艺。通过扫描电子显微镜获得图案特征的图像。使用图像中的图案化层的图案特征的位置来确定图案化层的位置。基于所确定的图案位置，以向量形式确定每个图案形成层相对于其它图案特征或图案化层的相对位置。叠加误差是根据相对位置与设计或模拟参考值的比较来确定的。可以通过利用图案对称性以高精度和精度测量覆盖层。

5. 发明授权

US06939649B2 Fabrication method of semiconductor integrated circuit device and mask 失效
标题翻译：半导体集成电路器件和掩模的制造方法
公开(公告)号：US06939649B2
公开(公告)日：2005-09-06
申请号：US10259397
申请日：2002-09-30
申请人： Shoji Hotta , Norio Hasegawa , Toshihiko Tanaka
发明人： Shoji Hotta , Norio Hasegawa , Toshihiko Tanaka
IPC分类号： G03F1/29 , G03F1/54 , G03F1/68 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F1/29
摘要： A method of fabrication of a semiconductor integrated circuit device uses a mark having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of light transmitted through the second light transmitting region relative to light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region. The second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first film and second is formed from a resist film.
摘要翻译：半导体集成电路器件的制造方法使用在掩模衬底的第一主表面上具有第一透光区域，设置在第一透光区域的周围的第二透光区域并允许反转透射通过第二透光区域的光相对于透过第一透光区域的光的相位，以及设置在第二透光区域周边的遮光区域。第二透光区域由沉积在掩模基板的第一主表面上的第一膜形成，所述遮光区域由通过所述第一膜沉积在掩模基板的第一主表面上的第二膜形成，并且至少所述第一膜和第二膜中的一个由抗蚀剂膜形成。

6. 发明授权

US06656646B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06656646B2
公开(公告)日：2003-12-02
申请号：US10195399
申请日：2002-07-16
申请人： Shoji Hotta , Norio Hasegawa
发明人： Shoji Hotta , Norio Hasegawa
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/56
摘要： A pattern accuracy of a semiconductor integrated circuit device is to be improved. When an ordinary photomask is to be replaced with a resist mask, in setting a planar size of a shielding pattern formed by resist film, a correction quantity L is subtracted from a planar size of a corresponding shielding pattern formed of metal. Conversely, when the resist mask is to be replaced with the ordinary mask, in setting a planar size of the shielding pattern formed of metal, the correction quantity L is added to the planar size of the corresponding shielding pattern formed by resist film.
摘要翻译：要提高半导体集成电路器件的图形精度。当普通光掩模用抗蚀剂掩模替代时，在设置由抗蚀剂膜形成的屏蔽图案的平面尺寸时，从由金属形成的对应的屏蔽图案的平面尺寸中减去校正量L. 相反，当用普通掩模替换抗蚀剂掩模时，在设置由金属形成的屏蔽图案的平面尺寸时，将校正量L加到由抗蚀剂膜形成的对应屏蔽图案的平面尺寸上。

7. 发明授权

US09297649B2 Pattern dimension measurement method and charged particle beam apparatus 有权
标题翻译：图案尺寸测量方法和带电粒子束装置
公开(公告)号：US09297649B2
公开(公告)日：2016-03-29
申请号：US14001433
申请日：2011-12-12
申请人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
发明人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
IPC分类号： G01B15/06 , G01N23/225 , H01J37/28 , H01J37/22 , G01N23/00 , H01J37/244
CPC分类号： G01B15/06 , G01N23/00 , H01J37/222 , H01J37/244 , H01J37/28 , H01J2237/24578 , H01J2237/2816 , H01J2237/2817
摘要： The present invention aims to provide a pattern dimension measurement method for accurately measuring an amount of shrinkage of a pattern that shrinks and an original dimension value before the shrinkage and a charged particle beam apparatus.In order to attain the above-mentioned object, there are proposed a pattern dimension measurement method and a charged particle beam apparatus that are characterized by: forming a thin film on a sample including the pattern after carrying out beam scanning onto a first portion of the pattern; acquiring a first measurement value by scanning a beam onto a region corresponding to the first portion on which the thin film is formed; acquiring a second measurement value by scanning a beam onto a second portion that has identical dimensions as those of the first portion on design data; and finding the amount of shrinkage of the pattern based on subtraction processing of subtracting the first measurement value from the second measurement value.
摘要翻译：本发明的目的在于提供一种图形尺寸测量方法，用于精确测量收缩的图案的收缩量和收缩前的原始尺寸值以及带电粒子束装置。为了实现上述目的，提出了一种图案尺寸测量方法和带电粒子束装置，其特征在于：在对包含图案的样品进行束扫描之后，在包含该图案的样品上形成薄膜至第一部分模式; 通过将光束扫描到与其上形成有薄膜的第一部分对应的区域来获取第一测量值; 通过将光束扫描到与设计数据上的第一部分具有相同尺寸的第二部分上来获取第二测量值; 并且基于从第二测量值减去第一测量值的减法处理来找出图案的收缩量。

8. 发明授权

US08671366B2 Estimating shape based on comparison between actual waveform and library in lithography process 有权
标题翻译：基于光刻过程中实际波形与库之间的比较估算形状
公开(公告)号：US08671366B2
公开(公告)日：2014-03-11
申请号：US13390354
申请日：2010-07-15
申请人： Maki Tanaka , Norio Hasegawa , Chie Shishido , Mayuka Osaki
发明人： Maki Tanaka , Norio Hasegawa , Chie Shishido , Mayuka Osaki
IPC分类号： G06F17/50
CPC分类号： G01B15/04 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape.As an illustrative embodiment to achieve the object, there are proposed a method of selecting a pattern by referring to a library, a method of creating a library by use of pattern cross-sectional shapes calculated through an exposure process simulation in advance, and a method for selecting a pattern shape stored in the library.
摘要翻译：本发明旨在提出一种库创建方法和图案形状估计方法，其中当基于实际波形和库之间的比较来估计形状时，可以适当地估计形状。作为实现该目的的说明性实施例，提出了通过参照库来选择图案的方法，通过使用预先通过曝光处理模拟计算的图案横截面形状来创建库的方法，以及方法用于选择存储在库中的图案形状。

9. 发明申请

US20140048706A1 PATTERN DIMENSION MEASUREMENT METHOD AND CHARGED PARTICLE BEAM APPARATUS 有权
标题翻译：图案尺寸测量方法和充电颗粒光束装置
公开(公告)号：US20140048706A1
公开(公告)日：2014-02-20
申请号：US14001433
申请日：2011-12-12
申请人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
发明人： Hiroki Kawada , Norio Hasegawa , Toru Ikegami
IPC分类号： G01N23/00
CPC分类号： G01B15/06 , G01N23/00 , H01J37/222 , H01J37/244 , H01J37/28 , H01J2237/24578 , H01J2237/2816 , H01J2237/2817
摘要： The present invention aims to provide a pattern dimension measurement method for accurately measuring an amount of shrinkage of a pattern that shrinks and an original dimension value before the shrinkage and a charged particle beam apparatus.In order to attain the above-mentioned object, there are proposed a pattern dimension measurement method and a charged particle beam apparatus that are characterized by: forming a thin film on a sample including the pattern after carrying out beam scanning onto a first portion of the pattern; acquiring a first measurement value by scanning a beam onto a region corresponding to the first portion on which the thin film is formed; acquiring a second measurement value by scanning a beam onto a second portion that has identical dimensions as those of the first portion on design data; and finding the amount of shrinkage of the pattern based on subtraction processing of subtracting the first measurement value from the second measurement value.
摘要翻译：本发明的目的在于提供一种图形尺寸测量方法，用于精确测量收缩的图案的收缩量和收缩前的原始尺寸值以及带电粒子束装置。为了实现上述目的，提出了一种图案尺寸测量方法和带电粒子束装置，其特征在于：在对包含图案的样品进行束扫描之后，在包含该图案的样品上形成薄膜至第一部分模式; 通过将光束扫描到与其上形成有薄膜的第一部分对应的区域来获取第一测量值; 通过将光束扫描到与设计数据上的第一部分具有相同尺寸的第二部分上来获取第二测量值; 并且基于从第二测量值减去第一测量值的减法处理来找出图案的收缩量。

10. 发明申请

US20130279793A1 IMAGE PROCESSING APPARATUS AND COMPUTER PROGRAM 有权
标题翻译：图像处理设备和计算机程序
公开(公告)号：US20130279793A1
公开(公告)日：2013-10-24
申请号：US13882141
申请日：2011-10-26
申请人： Yasutaka Toyoda , Norio Hasegawa , Ryoichi Matsuoka , Atsuko Yamaguchi
发明人： Yasutaka Toyoda , Norio Hasegawa , Ryoichi Matsuoka , Atsuko Yamaguchi
IPC分类号： G06T7/00
CPC分类号： G06T7/0004 , G06T7/001 , G06T2207/30141 , G06T2207/30152 , H01J37/222 , H01J37/28 , H01J2237/24578 , H01J2237/24592 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide an image processing apparatus and a computer program which detects a defect such as a scum at high speed and with high precision. In order to accomplish the above-described object, the present invention proposes an image processing apparatus and a computer program which acquires image data, and detects edge branch points from this image data. Here, at each of the edge branch points, an edge associated therewith branches off in at least three or more directions. According to this configuration, it becomes possible to detect a defect such as a scum without utilizing the reference-pattern image. As a consequence, it becomes possible to detect the scum at high speed and with high precision.
摘要翻译：本发明的目的是提供一种图像处理装置和计算机程序，其以高速和高精度检测浮渣等缺陷。为了实现上述目的，本发明提出一种图像处理装置和计算机程序，其获取图像数据，并从该图像数据检测边缘分支点。这里，在每个边缘分支点处，与其相关联的边缘在至少三个或更多个方向上分支。根据该结构，能够在不利用基准图案图像的情况下检测浮渣等缺陷。因此，可以高速，高精度地检测浮渣。

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