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1. 发明申请

US20140245273A1 PROTECTING THE INTEGRITY OF BINARY TRANSLATED CODE 有权
标题翻译：保护二进制翻译代码的完整性
公开(公告)号：US20140245273A1
公开(公告)日：2014-08-28
申请号：US13991894
申请日：2011-12-29
申请人： Shlomo Raikin , Lihu Rappoport , Joseph Nuzman
发明人： Shlomo Raikin , Lihu Rappoport , Joseph Nuzman
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/52 , G06F21/64
摘要： The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
摘要翻译：本文提供的技术涉及保护已经优化的原始代码的完整性。例如，处理器可以执行取出操作以从存储器获得指定的代码。在执行期间，代码可以被优化并存储在存储器的一部分中。处理器可以从存储器的一部分获得优化的代码。可以修改第一表的条目以指示特定代码和优化的代码之间的关系。可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。第二表中的一个或多个条目中的每一个可对应于第一表的条目。当第二表的一个或多个条目中的每一个有效时，处理器可以执行优化的代码。

2. 发明授权

US09027009B2 Protecting the integrity of binary translated code 有权
标题翻译：保护二进制翻译代码的完整性
公开(公告)号：US09027009B2
公开(公告)日：2015-05-05
申请号：US13991894
申请日：2011-12-29
申请人： Shlomo Raikin , Lihu Rappoport , Joseph Nuzman
发明人： Shlomo Raikin , Lihu Rappoport , Joseph Nuzman
IPC分类号： G06F9/45 , G06F21/64
CPC分类号： G06F8/41 , G06F8/52 , G06F21/64
摘要： The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
摘要翻译：本文提供的技术涉及保护已经优化的原始代码的完整性。例如，处理器可以执行取出操作以从存储器获得指定的代码。在执行期间，代码可以被优化并存储在存储器的一部分中。处理器可以从存储器的一部分获得优化的代码。可以修改第一表的条目以指示特定代码和优化的代码之间的关系。可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。第二表中的一个或多个条目中的每一个可对应于第一表的条目。当第二表的一个或多个条目中的每一个有效时，处理器可以执行优化的代码。

3. 发明授权

US09672019B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45 , G06F9/38 , G06F9/54 , G06F11/36
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

4. 发明申请

US20110167416A1 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 有权
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：US20110167416A1
公开(公告)日：2011-07-07
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

5. 发明申请

US20190102303A1 SOFTWARE-TRANSPARENT HARDWARE PREDICTOR FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION 审中-公开
公开(公告)号：US20190102303A1
公开(公告)日：2019-04-04
申请号：US15721249
申请日：2017-09-29
申请人： Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
发明人： Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
IPC分类号： G06F12/0831 , G06F12/084 , G06F12/0811
摘要： Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

6. 发明申请

US20150178202A1 METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION 有权
标题翻译：高速缓存行写回操作的方法和装置
公开(公告)号：US20150178202A1
公开(公告)日：2015-06-25
申请号：US14137432
申请日：2013-12-20
申请人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
发明人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F2212/1032 , G06F2212/222
摘要： An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.
摘要翻译：描述了用于执行高速缓存行回写操作的装置和方法。例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

7. 发明授权

US09830272B2 Cache memory staged reopen 有权
公开(公告)号：US09830272B2
公开(公告)日：2017-11-28
申请号：US13994639
申请日：2011-12-28
申请人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
发明人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
IPC分类号： G06F13/00 , G06F12/0891 , G11C7/10 , G06F1/32 , G06F12/0895
CPC分类号： G06F12/0891 , G06F1/3206 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G11C7/1072 , Y02D10/14 , Y02D50/20
摘要： An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.

8. 发明申请

US20160124802A1 MEMORY CORRUPTION DETECTION 有权
标题翻译：内存损坏检测
公开(公告)号：US20160124802A1
公开(公告)日：2016-05-05
申请号：US14531498
申请日：2014-11-03
申请人： Ron Gabor , Raanan Sade , Joseph Nuzman
发明人： Ron Gabor , Raanan Sade , Joseph Nuzman
IPC分类号： G06F11/10 , H03M13/00 , H03M13/09
CPC分类号： G06F11/10
摘要： Systems and methods for memory corruption detection. An example processing system comprises a processing core including a register to store a base address of a memory corruption detection (MCD) table. The processing core is configured to validate a pointer referenced by a memory access instruction, by comparing a first value derived from a first portion of the pointer to a second value stored in the MCD table at an offset referenced by a second portion of the pointer.
摘要翻译：内存损坏检测的系统和方法示例性处理系统包括处理核心，其包括用于存储存储器破坏检测（MCD）表的基址的寄存器。处理核心被配置为通过将由指针的第一部分导出的第一值与由指针的第二部分引用的偏移量相对应地存储在MCD表中的第二值进行比较来验证由存储器访问指令引用的指针。

9. 发明申请

US20130166846A1 Hierarchy-aware Replacement Policy 审中-公开
标题翻译：层次感知替代政策
公开(公告)号：US20130166846A1
公开(公告)日：2013-06-27
申请号：US13722607
申请日：2012-12-20
申请人： Jayesh Gaur , Mainak Chaudhuri , Sreenivas Subramoney , Nithiyanandan Bashyam , Joseph Nuzman
发明人： Jayesh Gaur , Mainak Chaudhuri , Sreenivas Subramoney , Nithiyanandan Bashyam , Joseph Nuzman
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0897 , G06F12/128
摘要： Some implementations disclosed herein provide techniques and arrangements for a hierarchy-aware replacement policy for a last-level cache. A detector may be used to provide the last-level cache with information about blocks in a lower-level cache. For example, the detector may receive a notification identifying a block evicted from the lower-level cache. The notification may include a category associated with the block. The detector may identify a request that caused the block to be filled into the lower-level cache. The detector may determine whether one or more statistics associated with the category satisfy a threshold. In response to determining that the one or more statistics associated with the category satisfy the threshold, the detector may send an indication to the last-level cache that the block is a candidate for eviction from the last-level cache.
摘要翻译：本文中公开的一些实施例提供了用于最后一级高速缓存的层次感知替换策略的技术和布置。可以使用检测器来向最后一级缓存提供关于下级缓存中的块的信息。例如，检测器可以接收识别从下级缓存中移出的块的通知。通知可以包括与块相关联的类别。检测器可以识别导致块被填充到下级高速缓存中的请求。检测器可以确定与该类别相关联的一个或多个统计信息是否满足阈值。响应于确定与类别相关联的一个或多个统计信息满足阈值，检测器可以向最后一级高速缓存发送指示该块是从最后一级高速缓存撤出的候选者的指示。

10. 发明申请

US20170177429A1 HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION 审中-公开
公开(公告)号：US20170177429A1
公开(公告)日：2017-06-22
申请号：US14977354
申请日：2015-12-21
申请人： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
发明人： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
IPC分类号： G06F11/07 , G06F3/06
CPC分类号： G06F11/0751 , G06F9/38 , G06F11/073 , G06F12/109 , G06F12/145 , G06F2212/1032 , G06F2212/1052 , G06F2212/656
摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

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