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1. 发明申请

US20130318292A1 CACHE MEMORY STAGED REOPEN 有权
公开(公告)号：US20130318292A1
公开(公告)日：2013-11-28
申请号：US13994639
申请日：2011-12-28
申请人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
发明人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
IPC分类号： G06F12/08 , G11C7/10
CPC分类号： G06F12/0891 , G06F1/3206 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G11C7/1072 , Y02D10/14 , Y02D50/20
摘要： An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state
摘要翻译：描述了一种装置。该装置包括具有两个或多个存储器块的高速缓冲存储器和耦合到高速缓存存储器的中央处理单元（CPU），以在从低功率状态退出时打开高速缓冲存储器内的第一存储器块

2. 发明授权

US09830272B2 Cache memory staged reopen 有权
公开(公告)号：US09830272B2
公开(公告)日：2017-11-28
申请号：US13994639
申请日：2011-12-28
申请人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
发明人： Iris Sorani , Larisa Novakovsky , Joseph Nuzman
IPC分类号： G06F13/00 , G06F12/0891 , G11C7/10 , G06F1/32 , G06F12/0895
CPC分类号： G06F12/0891 , G06F1/3206 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G11C7/1072 , Y02D10/14 , Y02D50/20
摘要： An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.

3. 发明授权

US09081687B2 Method and apparatus for MONITOR and MWAIT in a distributed cache architecture 有权
标题翻译：分布式缓存架构中MONITOR和MWAIT的方法和装置
公开(公告)号：US09081687B2
公开(公告)日：2015-07-14
申请号：US11966806
申请日：2007-12-28
申请人： Zeev Offen , Alon Naveh , Iris Sorani
发明人： Zeev Offen , Alon Naveh , Iris Sorani
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F12/0806 , G06F9/3009 , G06F12/084 , G06F2201/885 , G06F2212/1016 , G06F2212/284 , G06F2212/62
摘要： A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.
摘要翻译：公开了一种用于在分布式高速缓存架构中进行监视和等待的方法和装置。一个实施例包括向存储对应于该地址的数据的分布式高速缓存的一部分发送对地址的MONITOR请求的执行线程。在分布式缓存部分，MONITOR请求和关联的推测状态被本地记录在执行线程上。执行线程然后发出地址的MWAIT指令。在分布式缓存部分，为执行线程记录MWAIT和关联的等待触发状态。当在分布式高速缓存部分接收到与该地址匹配的写请求时，监视器 - 唤醒事件然后被发送到执行线程，并且用于该执行线程的分布式高速缓存部分处的关联监视状态可以被重置为空闲。

4. 发明申请

US20090172284A1 METHOD AND APPARATUS FOR MONITOR AND MWAIT IN A DISTRIBUTED CACHE ARCHITECTURE 有权
标题翻译：分布式高速缓存架构中监控和分布的方法和设备
公开(公告)号：US20090172284A1
公开(公告)日：2009-07-02
申请号：US11966806
申请日：2007-12-28
申请人： Zeev Offen , Alon Naveh , Iris Sorani
发明人： Zeev Offen , Alon Naveh , Iris Sorani
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0806 , G06F9/3009 , G06F12/084 , G06F2201/885 , G06F2212/1016 , G06F2212/284 , G06F2212/62
摘要： A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.
摘要翻译：公开了一种用于在分布式高速缓存架构中进行监视和等待的方法和装置。一个实施例包括向存储对应于该地址的数据的分布式高速缓存的一部分发送对地址的MONITOR请求的执行线程。在分布式缓存部分，MONITOR请求和关联的推测状态被本地记录在执行线程上。执行线程然后发出地址的MWAIT指令。在分布式缓存部分，为执行线程记录MWAIT和关联的等待触发状态。当在分布式高速缓存部分接收到与该地址匹配的写请求时，监视器 - 唤醒事件然后被发送到执行线程，并且用于该执行线程的分布式高速缓存部分处的关联监视状态可以被重置为空闲。

5. 发明授权

US09063729B2 Device, system and method of generating an execution instruction based on a memory-access instruction 有权
标题翻译：基于存储器访问指令生成执行指令的装置，系统和方法
公开(公告)号：US09063729B2
公开(公告)日：2015-06-23
申请号：US13591482
申请日：2012-08-22
申请人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
发明人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34 , G06F1/32 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种生成执行指令的装置，系统和方法。一些说明性实施例，我的包括基于表示存储器地址的存储器访问指令的存储器地址数据生成预定可执行格式的执行指令。描述和要求保护其他实施例。

6. 发明授权

US08281083B2 Device, system and method of generating an execution instruction based on a memory-access instruction 有权
标题翻译：基于存储器访问指令生成执行指令的装置，系统和方法
公开(公告)号：US08281083B2
公开(公告)日：2012-10-02
申请号：US11170115
申请日：2005-06-30
申请人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
发明人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
IPC分类号： G06F13/12
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种生成执行指令的装置，系统和方法。一些说明性实施例，我的包括基于表示存储器地址的存储器访问指令的存储器地址数据生成预定可执行格式的执行指令。描述和要求保护其他实施例。

7. 发明申请

US20130036317A1 Device, System And Method Of Generating An Execution Instruction Based On A Memory-Access Instruction 审中-公开
标题翻译：基于存储器访问指令生成执行指令的装置，系统和方法
公开(公告)号：US20130036317A1
公开(公告)日：2013-02-07
申请号：US13591482
申请日：2012-08-22
申请人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
发明人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
IPC分类号： G06F12/10 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种生成执行指令的装置，系统和方法。一些说明性实施例，我的包括基于表示存储器地址的存储器访问指令的存储器地址数据生成预定可执行格式的执行指令。描述和要求保护其他实施例。

8. 发明申请

US20070005910A1 Device, system and method of generating an execution instruction based on a memory-access instruction 有权
标题翻译：基于存储器访问指令生成执行指令的装置，系统和方法
公开(公告)号：US20070005910A1
公开(公告)日：2007-01-04
申请号：US11170115
申请日：2005-06-30
申请人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
发明人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
IPC分类号： G06F13/00
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种生成执行指令的装置，系统和方法。一些说明性实施例，我的包括基于表示存储器地址的存储器访问指令的存储器地址数据生成预定可执行格式的执行指令。描述和要求保护其他实施例。

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