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1. 发明申请

US20070096961A1 Signal processing device 审中-公开
标题翻译：信号处理装置
公开(公告)号：US20070096961A1
公开(公告)日：2007-05-03
申请号：US10580842
申请日：2004-10-14
申请人： Shiro Sakiyama , Masayoshi Kinoshita , Shiro Dosho
发明人： Shiro Sakiyama , Masayoshi Kinoshita , Shiro Dosho
IPC分类号： H03M7/30
CPC分类号： G10L21/04
摘要： In a signal processing device which performs data compression, a thinning circuit 1 generates thinned data by thinning input PCM data. For example, when a sampling rate fs of the PCM data (original data) is fs=10 Hz, thinned data of fs=1 Hz is generated. The determination circuit 2 controls the selection circuit 4 so that, based on the following expression: TOTAL1=|X(n)−X(n−1)|+|X(n−1)−X(n−2)|+ . . . +|X(n−8)−X(n−9)| if TOTAL1>C1, the input PCM data is selected, and if otherwise the thinned data is selected. The selected data and the determination result information of the determination circuit 2 are written into a memory 3. Therefore, data compression is performed with respect to original data with a simple circuit configuration and without losing required information of the original data.
摘要翻译：在执行数据压缩的信号处理装置中，细化电路1通过稀释输入PCM数据来生成稀疏数据。例如，当PCM数据（原始数据）的采样率fs为fs = 10Hz时，产生fs = 1Hz的稀疏数据。确定电路2控制选择电路4，使得基于以下表达式：<？in-line-formula description =“In-line formula”end =“lead”？> TOTAL1 = | X（n）-X（ n-1）| + | X（n-1）-X（n-2）| +。。。 + | X（n-8）-X（n-9）| <？in-line-formula description =“内联公式”end =“tail”？>如果TOTAL 1> C 1，输入的PCM数据选择，如果否则选择了稀疏数据。所选择的数据和确定电路2的确定结果信息被写入存储器3。因此，利用简单的电路配置对原始数据执行数据压缩，并且不丢失原始数据的所需信息。

2. 发明授权

US07808295B2 Multiphase level shift system 有权
标题翻译：多相电平转换系统
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00 , H03F3/66
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

3. 发明申请

US20090134931A1 MULTIPHASE LEVEL SHIFT SYSTEM 有权
标题翻译：多级水平移位系统
公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

4. 发明授权

US07920002B2 Pulse synthesis circuit 有权
标题翻译：脉冲合成电路
公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

5. 发明授权

US07876166B2 Coupled ring oscillator and method for laying out the same 有权
标题翻译：耦合环形振荡器及其布置方法
公开(公告)号：US07876166B2
公开(公告)日：2011-01-25
申请号：US12831715
申请日：2010-07-07
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

6. 发明授权

US07633421B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07633421B2
公开(公告)日：2009-12-15
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12）以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

7. 发明授权

US07453313B2 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US07453313B2
公开(公告)日：2008-11-18
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： G06F3/02
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

8. 发明授权

US07388405B2 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US07388405B2
公开(公告)日：2008-06-17
申请号：US11513239
申请日：2006-08-31
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03K19/094 , H03K19/0175 , H03B1/00
CPC分类号： H03K19/018571 , H03F1/0261 , H03F3/505 , H03F2200/18 , H04L25/028
摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.
摘要翻译：源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器使用输入数据信号从低电平变为高电平时的一个时钟周期。两个来源追随者在适当的时机运行。

9. 发明申请

US20060176091A1 Delay locked loop circuit 审中-公开
标题翻译：延时锁定回路电路
公开(公告)号：US20060176091A1
公开(公告)日：2006-08-10
申请号：US11289753
申请日：2005-11-30
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

10. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

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