专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06893937B1 Method for preventing borderless contact to well leakage 有权
标题翻译：防止无边界接触泄漏的方法
公开(公告)号：US06893937B1
公开(公告)日：2005-05-17
申请号：US10360746
申请日：2003-02-05
申请人： Shiqun Gu , Derryl J. Allman , Peter McGrath
发明人： Shiqun Gu , Derryl J. Allman , Peter McGrath
IPC分类号： H01L21/60 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/76224 , H01L21/76832 , H01L21/823475 , H01L21/823481
摘要： An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.
摘要翻译：本发明提供一种半导体芯片。通常，在基板上设置含有场氧化物的浅沟槽。在浅沟槽之间形成至少一个半导体器件。在至少一个半导体器件和场氧化物上形成氧化物层。在氧化物层上形成蚀刻停止层。在蚀刻停止层上形成层间电介质层。至少一个接触孔蚀刻穿过层间介电层，蚀刻停止层并且至少部分地穿过氧化物层。接触孔填充有导电材料。

2. 发明授权

US06551901B1 Method for preventing borderless contact to well leakage 有权
标题翻译：防止无边界接触泄漏的方法
公开(公告)号：US06551901B1
公开(公告)日：2003-04-22
申请号：US10006540
申请日：2001-11-30
申请人： Shiqun Gu , Derryl J. Allman , Peter McGrath
发明人： Shiqun Gu , Derryl J. Allman , Peter McGrath
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76224 , H01L21/76832 , H01L21/823475 , H01L21/823481
摘要： An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.
摘要翻译：本发明提供一种半导体芯片。通常，在基板上设置含有场氧化物的浅沟槽。在浅沟槽之间形成至少一个半导体器件。在至少一个半导体器件和场氧化物上形成氧化物层。在氧化物层上形成蚀刻停止层。在蚀刻停止层上形成层间电介质层。至少一个接触孔蚀刻穿过层间介电层，蚀刻停止层并且至少部分地穿过氧化物层。接触孔填充有导电材料。

3. 发明授权

US07098515B1 Semiconductor chip with borderless contact that avoids well leakage 有权
标题翻译：具有无边界接触的半导体芯片，避免漏电
公开(公告)号：US07098515B1
公开(公告)日：2006-08-29
申请号：US11104050
申请日：2005-04-11
申请人： Shioun Gu , Derryl J. Allman , Peter McGrath
发明人： Shioun Gu , Derryl J. Allman , Peter McGrath
IPC分类号： H01L23/52
CPC分类号： H01L21/823475 , H01L21/76224 , H01L21/76897 , H01L21/823481
摘要： An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.
摘要翻译：本发明提供一种半导体芯片。通常，在基板上设置含有场氧化物的浅沟槽。在浅沟槽之间形成至少一个半导体器件。在至少一个半导体器件和场氧化物上形成氧化物层。在氧化物层上形成蚀刻停止层。在蚀刻停止层上形成层间电介质层。至少一个接触孔蚀刻穿过层间介电层，蚀刻停止层并且至少部分地穿过氧化物层。接触孔填充有导电材料。

4. 发明授权

US06794304B1 Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process 有权
标题翻译：用于减少在双镶嵌工艺中产生的无边界通孔的微切削的方法和装置
公开(公告)号：US06794304B1
公开(公告)日：2004-09-21
申请号：US10631528
申请日：2003-07-31
申请人： Shiqun Gu , Masaichi Eda , Peter McGrath , Hong Lin , Jim Elmer
发明人： Shiqun Gu , Masaichi Eda , Peter McGrath , Hong Lin , Jim Elmer
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/76814 , H01L21/76826 , H01L21/76834
摘要： A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.
摘要翻译：制造半导体器件的方法包括提供由第一基本上导电的材料形成并具有上表面的第一元件。提供了与第一元件相邻的第二元件。第二元件由第一基本上不导电的材料形成。第二元件的上表面朝向第一元件的上表面向下倾斜。第二基本上非导电材料的第一层设置在第一元件的上表面和第二元件的上表面之上。第一层具有在垂直方向上的厚度，该厚度在第二元件的向下倾斜度上比在第一元件上的区域中大得多。进行蚀刻处理，使得该层在第一元件的上表面上方穿孔，并且在第二元件的向下倾斜的上表面上方的垂直较厚的区域中无孔。

5. 发明申请

US20070004191A1 Novel techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers 有权
标题翻译：碳纳米管从光掩模到晶圆的精密图案转移的新技术
公开(公告)号：US20070004191A1
公开(公告)日：2007-01-04
申请号：US11298274
申请日：2005-12-08
申请人： Shiqun Gu , Peter McGrath , James Elmer , Richard Carter
发明人： Shiqun Gu , Peter McGrath , James Elmer , Richard Carter
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , B82Y10/00 , H01L21/32136 , H01L21/32139 , H01L51/0018 , H01L51/0048 , Y10S977/742
摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.
摘要翻译：一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后，剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。

6. 发明授权

US06743669B1 Method of reducing leakage using Si3N4 or SiON block dielectric films 有权
标题翻译：使用Si3N4或SiON嵌段电介质薄膜减少泄漏的方法
公开(公告)号：US06743669B1
公开(公告)日：2004-06-01
申请号：US10164227
申请日：2002-06-05
申请人： Hong Lin , Shiqun Gu , Peter McGrath
发明人： Hong Lin , Shiqun Gu , Peter McGrath
IPC分类号： H01L218234
CPC分类号： H01L21/823481 , H01L21/3144 , H01L21/3185 , H01L27/0629
摘要： A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.
摘要翻译：在半导体处理中使用介电膜块来保护晶片的选定区域免受硅化。所选择的区域可以包括电阻器。在电阻器上形成第一层氧化物，并且在氧化物上设置包含SiON或Si3N4的第二层。对掩模进行图案化以允许在需要硅化物形成的区域进行蚀刻。氧化物层在蚀刻第二层期间用作蚀刻停止层。

7. 发明申请

US20160253760A1 A computer-implemented method for a social media mechanism to rate the liquidity of closed ended private investments 审中-公开
标题翻译：一种计算机实施的社交媒体机制评估封闭式私人投资流动性的方法
公开(公告)号：US20160253760A1
公开(公告)日：2016-09-01
申请号：US14767030
申请日：2014-05-08
申请人： Peter MCGRATH
发明人： Peter McGrath
IPC分类号： G06Q40/06 , G06Q50/18
CPC分类号： G06Q40/06 , G06F16/24578 , G06F16/9535 , G06Q50/01 , G06Q50/18 , H04L51/32
摘要： Closed ended private investment Funds may require liquidity rating as those Funds are not readily traded on any exchange or alternative trading system, but traded on limited access market. A new social media mechanism allows assigning liquidity rating to closed ended private investment funds based on potential institutional buyers interest, potential institutional buyers' capacity and Funds' restrictions.
摘要翻译：封闭式私人投资基金可能需要流动性评级，因为这些基金在任何交易所或替代交易系统上不容易交易，但在有限的进入市场上交易。新的社交媒体机制可以根据潜在的机构买家兴趣，潜在的机构买家的能力和资金的限制，将流动性评级分配给封闭式私人投资基金。

8. 发明授权

US09029215B2 Method of making an insulated gate semiconductor device having a shield electrode structure 有权
标题翻译：制造具有屏蔽电极结构的绝缘栅半导体器件的方法
公开(公告)号：US09029215B2
公开(公告)日：2015-05-12
申请号：US13471105
申请日：2012-05-14
申请人： Zia Hossain , Gordon M. Grivna , Duane B. Barber , Peter McGrath , Balaji Padmanabhan , Prasad Venkatraman
发明人： Zia Hossain , Gordon M. Grivna , Duane B. Barber , Peter McGrath , Balaji Padmanabhan , Prasad Venkatraman
IPC分类号： H01L21/336 , H01L29/66 , H01L29/40 , H01L29/78 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/4916 , H01L29/4933 , H01L29/66348 , H01L29/66363 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.
摘要翻译：在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。栅极电介质层沿沟槽的上表面形成。沿着栅极电介质层形成耐氧化间隔物。此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。氧化步骤增加了栅极电介质层的下部的厚度。在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

9. 发明申请

US20120052211A2 SOLDERABILITY ENHANCEMENT BY SILVER IMMERSION PRINTED CIRCUIT BOARD MANUFACTURE 有权
标题翻译：镀锡印刷电路板制造的焊接性提高
公开(公告)号：US20120052211A2
公开(公告)日：2012-03-01
申请号：US10099936
申请日：2002-03-13
申请人： Andrew Soutar , Peter McGrath
发明人： Andrew Soutar , Peter McGrath
IPC分类号： B05D1/18 , C23C18/38 , C23C18/42 , C23C18/31
CPC分类号： H05K3/244 , B05D5/12 , C23C18/42 , Y10T29/4913 , Y10T29/49144
摘要： A process used during manufacture of printed circuit boards comprises protecting metal pads and/or through-holes to provide a tarnish-resistant and solderable coating. In the method, the pads and/or through-holes are bright-etched, metal plated, preferably by an immersion process, and treated with a tarnish inhibitor. The tarnish inhibitor may be incorporated into the immersion plating bath. The metal plating is usually with silver or bismuth and the pads and/or through-holes comprise copper.
摘要翻译：在制造印刷电路板期间使用的方法包括保护金属焊盘和/或通孔以提供耐光泽和可焊接的涂层。在该方法中，优选通过浸渍工艺对焊盘和/或通孔进行光刻蚀，金属镀覆，并用晦暗抑制剂处理。可以将沉淀抑制剂掺入浸镀浴中。金属镀层通常具有银或铋，并且焊盘和/或通孔包括铜。

10. 发明申请

US20160253762A1 A method for a social media mechanism to facilitate collaboration and information exchange for private investment funds 审中-公开
标题翻译：一种促进私人投资基金合作和信息交流的社交媒体机制的方法
公开(公告)号：US20160253762A1
公开(公告)日：2016-09-01
申请号：US14762871
申请日：2014-06-27
申请人： Peter MCGRATH
发明人： Peter McGrath
IPC分类号： G06Q50/00 , G06F17/30 , G06Q40/06
CPC分类号： G06Q40/06 , G06F16/24578 , G06F16/9535 , G06Q50/01 , G06Q50/18 , H04L51/32
摘要： Unlike publicly traded securities, current information and documents on private investments are not often in the public domain. Also, a typical private investment has a small existing or potential investor base worldwide. Further, institutional and private investors in private investments rarely publicize or disclose their interest or investments in private investments. In addition, at any given time only a small number of relevant institutional investors or analysts are likely to be interested in buying, selling or diligencing a specific private investment. Anonymously gaining access to such information or finding contacts willing to collaborate on diligence research, buying or selling and analysis of any specific private investment is likely to be onerous if not impossible. Even when an industry participant has an existing business relationship with the relevant business contact, details of the private investments your business connections are currently diligencing, have interest in buying or selling are often held in private confidence.To ease such barriers and to enhance exchange and collaboration amongst investment professionals, this new invention allows investors to openly share what private investments they are buying, selling, diligencing or following since the platform's tailored privacy settings assures preserved anonymity if so chosen. The invented mechanism facilitates free communication, collaboration on due diligence analysis, buying and selling, access to and the ability to freely share information which may be confidential in nature through the use of social media tools, in a privacy controlled computer network environment.
摘要翻译：与上市证券不同，目前关于私人投资的信息和文件并不常见于公共领域。此外，典型的私人投资在全球拥有一小部分现有或潜在的投资者基础。此外，私人投资的机构和私人投资者很少宣传或披露其对私人投资的兴趣或投资。此外，在任何时候，只有少数相关的机构投资者或分析师可能有兴趣购买，出售或扩张特定的私人投资。匿名访问这些信息或找到愿意合作进行勤奋研究，购买或销售和分析任何特定私人投资的联系人，如果不是不可能，可能是繁重的。即使行业参与者与相关业务联系人存在现有的业务关系，您的业务关系目前稀释的私人投资的细节，对买卖的兴趣往往是以私人信心。为了缓解这种障碍，加强投资专业人士之间的交流与合作，这项新发明使投资者可以公开分享他们购买，出售，稀释或追踪的私人投资，因为平台的定制隐私设置保证了如果选择了保留匿名的隐私设置。本发明的机制有助于在隐私控制的计算机网络环境中，通过使用社交媒体工具实现自由沟通，协作，尽职调查分析，购买和销售，访问和自由分享可能是机密的信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式