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1. 发明授权

US07831949B2 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法，设计装置，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US07831949B2
公开(公告)日：2010-11-09
申请号：US11819573
申请日：2007-06-28
申请人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

2. 发明申请

US20110012260A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：设计半导体集成电路的方法，设计器件，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US20110012260A1
公开(公告)日：2011-01-20
申请号：US12892273
申请日：2010-09-28
申请人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： H01L23/485 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

3. 发明申请

US20080022252A1 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法，设计装置，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US20080022252A1
公开(公告)日：2008-01-24
申请号：US11819573
申请日：2007-06-28
申请人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： G06F17/50 , H01L23/48
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

4. 发明授权

US07565637B2 Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same 失效
标题翻译：设计用于半导体器件的封装的方法，用于执行该封装的布局设计工具以及使用其的半导体器件的制造方法
公开(公告)号：US07565637B2
公开(公告)日：2009-07-21
申请号：US11592168
申请日：2006-11-03
申请人： Koichi Seko , Shinya Tokunaga
发明人： Koichi Seko , Shinya Tokunaga
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/66 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and an internal connection terminal connected to the chip, the method comprising: setting an acceptable noise value of the package; designing a package layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on package layout data so that an amount of noises remains within a range which is set beforehand, on the basis of the package layout data obtained in the designing process of the package layout.
摘要翻译：一种用于设计包括具有布线图案的封装基板，安装在封装基板上的芯片和覆盖封装基板和芯片的密封树脂的封装的半导体器件的封装设计方法，以及包括外部连接端子和连接到芯片的内部连接端子，所述方法包括：设置所述封装的可接受的噪声值; 在封装基板与芯片之间的连接信息的基础上设计封装布局; 并且基于在包装布局的设计过程中获得的包装布局数据，对包装布局数据执行优化，使得噪声量保持在预先设定的范围内。

5. 发明申请

US20110210453A1 METHOD FOR DESIGNING ELECTRONIC SYSTEM 审中-公开
标题翻译：设计电子系统的方法
公开(公告)号：US20110210453A1
公开(公告)日：2011-09-01
申请号：US13107269
申请日：2011-05-13
申请人： Keiichi KUSUMOTO , Shinya Tokunaga , Mitumi Ito , Koichi Seko
发明人： Keiichi KUSUMOTO , Shinya Tokunaga , Mitumi Ito , Koichi Seko
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： G06F17/5068 , H05K3/0005
摘要： When an electronic system is designed, then if an integrated circuit chip (LSI), a package (PKG), and a printed circuit board (PCB) are designed separately and in parallel, it will be found near the end of the design process that a satisfactory electrical characteristic is not achieved. Therefore, a design procedure of each part (e.g., an LSI, a PKG, a PCB, etc.) is decided, and allocation of resources to a part which is designed with a higher priority is decided, and thereafter, the other parts start to be designed. Therefore, a basic interconnect distribution for a circuit board is calculated based on a prediction function for predicting an interconnect distribution for the circuit board using design information of the circuit board as input data, and is output.
摘要翻译：当设计电子系统时，如果集成电路芯片（LSI），封装（PKG）和印刷电路板（PCB）被单独并行设计，则将在设计过程结束时发现不能达到令人满意的电气特性。因此，决定各部分（例如，LSI，PKG，PCB等）的设计程序，并且决定对设计为较高优先级的部分的资源分配，其后的部分开始设计。因此，基于用于使用电路板的设计信息预测电路板的互连分布的预测功能作为输入数据来计算电路板的基本互连分布，并被输出。

6. 发明申请

US20070105271A1 Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same 失效
标题翻译：设计用于半导体器件的封装的方法，用于执行该封装的布局设计工具以及使用其的半导体器件的制造方法
公开(公告)号：US20070105271A1
公开(公告)日：2007-05-10
申请号：US11592168
申请日：2006-11-03
申请人： Koichi Seko , Shinya Tokunaga
发明人： Koichi Seko , Shinya Tokunaga
IPC分类号： H01L21/00
CPC分类号： G06F17/5068 , H01L23/66 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and an internal connection terminal connected to the chip, the method comprising: setting an acceptable noise value of the package; designing a package layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on package layout data so that an amount of noises remains within a range which is set beforehand, on the basis of the package layout data obtained in the designing process of the package layout.
摘要翻译：一种用于设计包括具有布线图案的封装基板，安装在封装基板上的芯片和覆盖封装基板和芯片的密封树脂的封装的半导体器件的封装设计方法，以及包括外部连接端子和连接到芯片的内部连接端子，所述方法包括：设置所述封装的可接受的噪声值; 在封装基板与芯片之间的连接信息的基础上设计封装布局; 并且基于在包装布局的设计过程中获得的包装布局数据，对包装布局数据执行优化，使得噪声量保持在预先设定的范围内。

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