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1. 发明授权

US07831949B2 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法，设计装置，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US07831949B2
公开(公告)日：2010-11-09
申请号：US11819573
申请日：2007-06-28
申请人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

2. 发明申请

US20110012260A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：设计半导体集成电路的方法，设计器件，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US20110012260A1
公开(公告)日：2011-01-20
申请号：US12892273
申请日：2010-09-28
申请人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： H01L23/485 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

3. 发明申请

US20080022252A1 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法，设计装置，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US20080022252A1
公开(公告)日：2008-01-24
申请号：US11819573
申请日：2007-06-28
申请人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： G06F17/50 , H01L23/48
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

4. 发明授权

US06988254B2 Method for designing semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US06988254B2
公开(公告)日：2006-01-17
申请号：US10601287
申请日：2003-06-20
申请人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
发明人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其能够通过在不减少元件排列所需的有效面积的情况下减少IR降低对定时的影响而实现近似于实际操作的定时仿真或者焊盘的数量可以使用电源垫以外的处理时间。在FF驱动能力改变过程中，具有大于从电源电压中的IR降低到理想电源电压的状态的转变时间的延迟时间的触发器被替换为任意翻转 -flop。因此，考虑到IR降低的延迟库可以仅在触发器中产生，从而能够减少库的生产时间并提高延迟计算过程中的延迟时间的计算精度。此外，替代具有低驾驶能力的触发器使得能够减小面积。

5. 发明授权

US06795802B2 Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method 失效
标题翻译：用于计算LSI的时间恶化裕量的装置和方法，以及LSI检查方法
公开(公告)号：US06795802B2
公开(公告)日：2004-09-21
申请号：US09810518
申请日：2001-03-19
申请人： Hirokazu Yonezawa , Yoshiyuki Kawakami , Nobufusa Iwanishi
发明人： Hirokazu Yonezawa , Yoshiyuki Kawakami , Nobufusa Iwanishi
IPC分类号： G06F1710
CPC分类号： G01R31/318371 , G01R31/287 , G01R31/318342
摘要： The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305. A delay deterioration margin amount calculating part 104 calculates a delay deterioration margin amount by using the delay deterioration margin 305 as a derating factor G. Furthermore, a inspection operation frequency calculating part 105 calculates an operation frequency for inspection using the delay deterioration margin 305 as a derating factor G.
摘要翻译：本发明使得可以简化地获得包括老化劣化余地的老化退化裕度量。此外，为了考虑老化劣化的适当检查，延迟劣化率预测部101基于LSI设计信息301，对各信号路径输出恶化前的信号路径延迟信息302和信号路径延迟劣化率信息303。延迟与延迟劣化率分析部分102基于该信息输出延迟与延迟退化率关系信息304，其显示延迟和延迟退化率之间的相关性。延迟劣化率提取部分103提取预定信号路径的延迟劣化率，并将其作为延迟劣化边缘305输出。延迟劣化边际量计算部分104通过使用延迟劣化边缘305作为降额来计算延迟劣化边际量另外，检查动作频率计算部105使用延迟劣化余量305作为降额因子G来计算检查用的操作频率。

6. 发明授权

US5761081A Method of evaluating signal propagation delay in logic integrated circuit 失效
标题翻译：评估逻辑集成电路中信号传播延迟的方法
公开(公告)号：US5761081A
公开(公告)日：1998-06-02
申请号：US638079
申请日：1996-04-26
申请人： Yasuhiro Tomita , Nobufusa Iwanishi , Ryuichi Yamaguchi , Hisakazu Edamatsu
发明人： Yasuhiro Tomita , Nobufusa Iwanishi , Ryuichi Yamaguchi , Hisakazu Edamatsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.
摘要翻译：评估具有第一反相器单元和通过单元间线连接的第二反相器单元的逆变器链中的信号传播延迟。为了确保总是将第一反相器单元延迟评估为正（A），将第一反相器单元的输入引脚电压的增加的逻辑阈值电压设置为低于第一反相器单元的开关阈值电压的电压和（B）将第一反相器单元的输入引脚电压降低的逻辑阈值电压设定为高于第一反相器单元的开关阈值电压的电压。类似地，确定用于第二逆变器单元的输入引脚电压的增加和减小的逻辑阈值电压。此外，为了保证细胞间线延迟始终被评估为正，使得第一反相器单元的输出引脚电压的逻辑阈值电压与第二反相器单元的输入引脚电压的逻辑阈值电压一致。

7. 发明授权

US07925998B2 Delay calculating method in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的延迟计算方法
公开(公告)号：US07925998B2
公开(公告)日：2011-04-12
申请号：US11296640
申请日：2005-12-08
申请人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
摘要翻译：在功能表达式中预先获得单元的输入引脚电容，并且以这样的方式计算延迟，使得在每种情况下以输入转换和驱动负载电容的功能计算输入引脚电容。在单元特征处理中，获得在输入端子的电压值达到基准电压之前进入输入端子的电流的总体积，从而可以获得接近实际输入引脚电容的值。

8. 发明申请

US20050232066A1 Method for characterizing cells with consideration for bumped waveform and delay time calculation method for semiconductor integrated circuits using the same 审中-公开
标题翻译：考虑使用其的半导体集成电路的凸起波形和延迟时间计算方法来表征单元的方法
公开(公告)号：US20050232066A1
公开(公告)日：2005-10-20
申请号：US11108696
申请日：2005-04-19
申请人： Noriko Ishibashi , Naoki Amekawa , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Naoki Amekawa , Nobufusa Iwanishi
IPC分类号： G06F17/50 , G11C8/00
CPC分类号： G06F17/5036
摘要： An effective input terminal capacitance which is effectively equivalent to a cell in which a waveform distortion is caused due to the Miller effect and a drive load connected to the cell is calculated in advance, and the cell and the drive load are replaced by the calculated effective input terminal capacitance, while considering that the Miller effect is caused according to the size of the drive load driven by a delay time calculation subject circuit, such as a cell, or the like, and a distortion occurs in input and output waveforms of the delay time calculation subject circuit due to the Miller effect. Thereafter, a circuit simulation is carried out using the effective input terminal capacitance. A resultant effective input terminal capacitance value is characterized as a function of an input slope waveform and the drive load and converted to table data.
摘要翻译：预先计算有效输入端子电容，其有效地等效于由于米勒效应引起的波形失真的单元和连接到单元的驱动负载的单元，并且计算单元和驱动负载被计算的有效输入端子电容，同时考虑到由延迟时间计算对象电路（例如单元等）驱动的驱动负载的大小引起米勒效应，并且在延迟的输入和输出波形中发生失真时间计算主题电路由于米勒效应。此后，使用有效输入端子电容进行电路仿真。合成的有效输入端电容值的特征在于输入斜率波形和驱动负载的函数，并转换为表数据。

9. 发明授权

US06629299B1 Delay library representation method, delay library generation method and delay calculation method using the delay library 失效
标题翻译：延迟库表示方法，延迟库生成方法和使用延迟库的延迟计算方法
公开(公告)号：US06629299B1
公开(公告)日：2003-09-30
申请号：US09593605
申请日：2000-06-12
申请人： Nobufusa Iwanishi
发明人： Nobufusa Iwanishi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： In order to perform precision delay calculation of a signal of small signal-swing, a delay library in consideration of the small signal-swing making no full swing is generated. It is assumed that a signal having a rising edge and a step waveform which lags the rising edge by a fixed time interval and a signal having a step waveform and a falling edge which lags the step waveform by the fixed time interval are entered as an input signal to a cell. The driving ability of the cell is represented by a function or in a table having as parameters the slews of the rising and falling edges, the fixed time interval and the load capacitance driven by the cell.
摘要翻译：为了进行小信号摆动的信号的精度延迟计算，考虑到小信号摆幅不产生全摆幅的延迟库。假设将具有上升沿和阶跃波形的信号以固定的时间间隔落在上升沿和具有阶梯波形和下降沿的信号作为输入而被输入到步进波形信号到一个单元格。单元的驱动能力由功能表或具有上升沿和下降沿的摆动，固定时间间隔和由单元驱动的负载电容的参数的表示。

10. 发明授权

US07107557B2 Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit 有权
公开(公告)号：US07107557B2
公开(公告)日：2006-09-12
申请号：US10403285
申请日：2003-04-01
申请人： Nobufusa Iwanishi
发明人： Nobufusa Iwanishi
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： In a circuit simulation step, a cell transistor level net list is input, the slew of an input signal waveform and the magnitude of a load capacitance connected to a cell output terminal are varied for each cell, to perform a circuit simulation of each cell for obtaining an output signal waveform. Next, in a dependence table generation step, the dependence of the output signal waveform slew upon the input slew rate and the load capacitance is calculated for each cell, the dependence thus calculated is compared with a predetermined threshold level, and according to the dependence level, a delay calculation expression with consideration taken to the delay of signal propagation between the cell input and output terminals and another without such consideration are selectively used. Accordingly, the delay times of the cells forming a semiconductor integrated circuit can be calculated at high accuracy and at high processing speed.

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