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1. 发明授权

US08232556B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08232556B2
公开(公告)日：2012-07-31
申请号：US13099840
申请日：2011-05-03
申请人： Ryo Arasawa , Aya Miyazaki , Shigeharu Monoe , Shunpei Yamazaki
发明人： Ryo Arasawa , Aya Miyazaki , Shigeharu Monoe , Shunpei Yamazaki
IPC分类号： H01L27/14
CPC分类号： H01L27/1266 , H01L27/124 , H01L29/78603 , H01L29/78606
摘要： An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.
摘要翻译：本发明的目的是提供一种半导体器件，其中即使当外部施加诸如弯曲的物理力在半导体器件中产生应力时，诸如晶体管的元件的损伤也减小。半导体器件包括：设置在基板上的沟道形成区域和杂质区域的半导体膜，设置在沟道形成区域上的栅极绝缘膜之间的第一导电膜，设置成覆盖的第一层间绝缘膜所述第一导电膜，设置在所述第一层间绝缘膜上以与所述杂质区的至少一部分重叠的第二导电膜，设置在所述第二导电膜上的第二层间绝缘膜，以及设置在所述第二导电膜上的第二导电膜层间绝缘膜，以通过开口与杂质区电连接。

2. 发明申请

US20120133839A1 SOURCE LINE DRIVING CIRCUIT, ACTIVE MATRIX TYPE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：源线驱动电路，有源矩阵型显示装置及其驱动方法
公开(公告)号：US20120133839A1
公开(公告)日：2012-05-31
申请号：US13368374
申请日：2012-02-08
申请人： Mitsuaki OSAME , Aya MIYAZAKI
发明人： Mitsuaki OSAME , Aya MIYAZAKI
IPC分类号： H04N5/268
CPC分类号： G09G3/3688 , G09G3/3275 , G09G2310/0235
摘要： If the frequency of a clock signal is increased, the pulse width of a sampling pulse is decreased, and the amount of time for a video signal to be written to a source line is inadequate. Sampling pulses (sam) rise sequentially in synchronization with the rise of a start pulse (SP). As the start pulse (SP) rises, synchronized with the rise of clock signals (CK, CKB), the sampling pulses (sam) fall off sequentially, delayed by half the period of the clock signals (CK, CKB) for every step. As a result, the sampling pulses (sam) with a pulse width longer than one period of the clock signals (CK, CKB) are generated. In a period Ta, a desired video signal (VIDEO) is written to its corresponding source line. In this way, the time for half a period of the clock signal can be secured for writing to the source line.
摘要翻译：如果时钟信号的频率增加，则采样脉冲的脉冲宽度减小，并且视频信号写入源极线的时间量不足。采样脉冲（sam）与起始脉冲（SP）的上升同步上升。随着起始脉冲（SP）上升，与时钟信号（CK，CKB）的上升同步，采样脉冲（sam）依次下降，延迟了每一步的时钟信号（CK，CKB）周期的一半。结果，产生脉冲宽度大于时钟信号（CK，CKB）的一个周期的采样脉冲（sam）。在周期Ta中，将期望的视频信号（VIDEO）写入其对应的源极线。以这种方式，可以确保时钟信号的半个周期的时间用于写入源极线。

3. 发明授权

US08018776B2 Verification method for nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的验证方法
公开(公告)号：US08018776B2
公开(公告)日：2011-09-13
申请号：US12836243
申请日：2010-07-14
申请人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译：本发明提供了以低功耗工作的非易失性半导体存储器件。在非易失性半导体存储器件中，多个非易失性存储元件串联连接。多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位的第一次读取被使用。

4. 发明申请

US20110204424A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110204424A1
公开(公告)日：2011-08-25
申请号：US13099840
申请日：2011-05-03
申请人： Ryo ARASAWA , Aya MIYAZAKI , Shigeharu MONOE , Shunpei YAMAZAKI
发明人： Ryo ARASAWA , Aya MIYAZAKI , Shigeharu MONOE , Shunpei YAMAZAKI
IPC分类号： H01L29/78
CPC分类号： H01L27/1266 , H01L27/124 , H01L29/78603 , H01L29/78606
摘要： An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.
摘要翻译：本发明的目的是提供一种半导体器件，其中即使当外部施加诸如弯曲的物理力在半导体器件中产生应力时，诸如晶体管的元件的损伤也减小。半导体器件包括：设置在基板上的沟道形成区域和杂质区域的半导体膜，设置在沟道形成区域上的栅极绝缘膜之间的第一导电膜，设置成覆盖的第一层间绝缘膜所述第一导电膜，设置在所述第一层间绝缘膜上以与所述杂质区的至少一部分重叠的第二导电膜，设置在所述第二导电膜上的第二层间绝缘膜，以及设置在所述第二导电膜上的第二导电膜层间绝缘膜，以通过开口与杂质区电连接。

5. 发明授权

US07961525B2 Method for deleting data from NAND type nonvolatile memory 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US07961525B2
公开(公告)日：2011-06-14
申请号：US12491395
申请日：2009-06-25
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

6. 发明授权

US07692973B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07692973B2
公开(公告)日：2010-04-06
申请号：US11727209
申请日：2007-03-23
申请人： Aya Miyazaki , Mitsuaki Osame , Hiroyuki Miyake , Shunpei Yamazaki
发明人： Aya Miyazaki , Mitsuaki Osame , Hiroyuki Miyake , Shunpei Yamazaki
IPC分类号： G11C11/03
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译：提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。源区和漏区中的每一个通过半导体杂质区电连接到擦除线。

7. 发明申请

US20090257283A1 METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US20090257283A1
公开(公告)日：2009-10-15
申请号：US12491395
申请日：2009-06-25
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

8. 发明申请

US20070230254A1 Method for deleting data from NAND type nonvolatile memory 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US20070230254A1
公开(公告)日：2007-10-04
申请号：US11716672
申请日：2007-03-12
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

9. 发明申请

US20070230249A1 Verification method for nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的验证方法
公开(公告)号：US20070230249A1
公开(公告)日：2007-10-04
申请号：US11729216
申请日：2007-03-28
申请人： Hiroyuki Miyaki , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyaki , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译：本发明提供了以低功耗工作的非易失性半导体存储器件。在非易失性半导体存储器件中，多个非易失性存储元件串联连接。多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位的第一次读取被使用。

10. 发明授权

US06577356B2 Plasma addressed liquid crystal display device and method for fabricating the same 有权
标题翻译：等离子体寻址液晶显示装置及其制造方法
公开(公告)号：US06577356B2
公开(公告)日：2003-06-10
申请号：US09730743
申请日：2000-12-07
申请人： Noriaki Onishi , Aya Miyazaki
发明人： Noriaki Onishi , Aya Miyazaki
IPC分类号： G02F1133
CPC分类号： G02F1/13334 , G02F1/1337 , G02F2201/086
摘要： The liquid crystal display (LCD) device of the invention includes: a substrate; a dielectric layer; a liquid crystal layer sandwiched by the substrate and the dielectric layer; a plurality of stripe-shaped electrodes formed on a surface of the substrate facing the liquid crystal layer to extend in parallel with a first direction; and a plurality of stripe-shaped plasma channels formed to face the plurality of electrodes with the liquid crystal layer and the dielectric layer therebetween to extend in parallel with a second direction different from the first direction. The dielectric layer or an alignment layer formed on a surface of the dielectric layer facing the liquid crystal layer selectively attenuates ultraviolet rays emitted from the plasma channels.
摘要翻译：本发明的液晶显示（LCD）装置包括：基板; 电介质层; 夹在基板和电介质层之间的液晶层; 多个条形电极，形成在所述基板的面向所述液晶层的表面上，以与第一方向平行地延伸; 以及多个条形等离子体通道，其形成为与液晶层和介电层面对多个电极，以与第一方向不同的第二方向平行延伸。形成在面向液晶层的电介质层的表面上的介电层或取向层选择性地衰减从等离子体通道发射的紫外线。

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