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1. 发明授权

US07848177B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07848177B2
公开(公告)日：2010-12-07
申请号：US12269098
申请日：2008-11-12
申请人： Shinya Kajiyama , Yutaka Shinagawa , Makoto Mizuno , Hideo Kasai , Takao Watanabe , Riichiro Takemura , Tomonori Sekiguchi
发明人： Shinya Kajiyama , Yutaka Shinagawa , Makoto Mizuno , Hideo Kasai , Takao Watanabe , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C8/00
CPC分类号： G11C7/1039 , G11C7/1075 , G11C16/26
摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.
摘要翻译：半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

2. 发明申请

US20050180041A1 Disk storage systems 失效
标题翻译：磁盘存储系统
公开(公告)号：US20050180041A1
公开(公告)日：2005-08-18
申请号：US11033258
申请日：2005-01-12
申请人： Shinya Kajiyama , Hiroyasu Yoshizawa , Yoichiro Kobayashi , Ichiro Somada
发明人： Shinya Kajiyama , Hiroyasu Yoshizawa , Yoichiro Kobayashi , Ichiro Somada
IPC分类号： G11B5/02 , G11B5/09 , H01L43/08
CPC分类号： G11B5/09 , G11B5/012
摘要： The present invention provides a disk storage system with a low error rate, which is suitable for reduction in size. The other end of the signal line, which is connected with a read head at one end, is connected with a head bias circuit to apply a sense current to the read head and a pair of first and second capacitance elements for allowing the read signal element formed by the read head to pass, a loop is provided for amplifying the read signal obtained through the first and second capacitance elements by supplying the read signal to an input terminal of a differential amplifying circuit and for converting the amplified signal into the current by transconductance and providing a positive feedback of the amplified signal to the input terminal of the differential amplifying circuit.
摘要翻译：本发明提供一种低误码率的盘存储系统，适合于减小尺寸。在一端与读头连接的信号线的另一端与头偏置电路连接，以将读出电流施加到读取头和一对第一和第二电容元件，以允许读取信号元件由读头通过，提供一个环路，用于通过将读信号提供给差分放大电路的输入端来放大通过第一和第二电容元件获得的读信号，并将放大的信号转换成电流通过跨导并将放大信号的正反馈提供给差分放大电路的输入端。

3. 发明申请

US20090024810A1 Memory area management method 审中-公开
标题翻译：内存区管理方法
公开(公告)号：US20090024810A1
公开(公告)日：2009-01-22
申请号：US12219051
申请日：2008-07-15
申请人： Daisuke Ito , Shinji Fujiwara , Kazuo Otsuga , Shinya Kajiyama
发明人： Daisuke Ito , Shinji Fujiwara , Kazuo Otsuga , Shinya Kajiyama
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： In a storage device, a method is provided for preventing the risk of data loss and a significant decrease of writing speed due to area shrinkage when erased erase blocks have become fewer. A process of allocating a new page includes determining whether the length of a deallocated pages list is longer than n pages. If the list length is longer, one page is allocated from the deallocated pages list. If the list length is shorter, a capacity shortage error returns. Deleting a file using an erased pages list includes determining whether a page to be processed is emptied by deleting the file. If not so, the file is deleted from the page. If so, the contents of the last page-a in occupied pages are copied to the page, the page-a is written with data for erasure, and any erase block included in the page-a is made erasable.
摘要翻译：在存储装置中，提供了一种防止数据丢失的风险的方法，并且当擦除擦除块变得更少时，由于面积缩小而显着降低写入速度。分配新页面的过程包括确定取消分配页面列表的长度是否长于n页。如果列表长度较长，则从取消分配的页面列表中分配一个页面。如果列表长度较短，则容量短缺错误返回。使用删除的页面列表删除文件包括确定要处理的页面是否通过删除文件被清空。如果不是这样，该文件将从页面中删除。如果是这样，被占用页面中的最后一页的内容被复制到页面，页面a被写入用于擦除的数据，并且包含在页面a中的任何擦除块被擦除。

4. 发明授权

US07082004B2 Disk storage systems 失效
标题翻译：磁盘存储系统
公开(公告)号：US07082004B2
公开(公告)日：2006-07-25
申请号：US11033258
申请日：2005-01-12
申请人： Shinya Kajiyama , Hiroyasu Yoshizawa , Yoichiro Kobayashi , Ichiro Somada
发明人： Shinya Kajiyama , Hiroyasu Yoshizawa , Yoichiro Kobayashi , Ichiro Somada
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B5/012
摘要： The present invention provides a disk storage system with a low error rate, which is suitable for reduction in size. The other end of the signal line, which is connected with a read head at one end, is connected with a head bias circuit to apply a sense current to the read head and a pair of first and second capacitance elements for allowing the read signal element formed by the read head to pass, a loop is provided for amplifying the read signal obtained through the first and second capacitance elements by supplying the read signal to an input terminal of a differential amplifying circuit and for converting the amplified signal into the current by transconductance and providing a positive feedback of the amplified signal to the input terminal of the differential amplifying circuit.
摘要翻译：本发明提供一种低误码率的盘存储系统，适合于减小尺寸。在一端与读头连接的信号线的另一端与头偏置电路连接，以将读出电流施加到读取头和一对第一和第二电容元件，以允许读取信号元件由读头通过，提供一个环路，用于通过将读信号提供给差分放大电路的输入端来放大通过第一和第二电容元件获得的读信号，并将放大的信号转换成电流通过跨导并将放大信号的正反馈提供给差分放大电路的输入端。

5. 发明授权

US08823349B2 Switching regulation controller, switching regulator and controlling method for switching regulation 有权
标题翻译：开关调节控制器，开关调节器和开关调节控制方式
公开(公告)号：US08823349B2
公开(公告)日：2014-09-02
申请号：US13095711
申请日：2011-04-27
申请人： Shinya Kajiyama
发明人： Shinya Kajiyama
IPC分类号： G05F1/00
CPC分类号： H02M3/157
摘要： A switching regulation controller for driving a switch circuit included in a switching regulator which converts an input voltage to a target voltage, and outputs the target voltage. The switching regulation controller detects an error between the output voltage and the target voltage, and uses the detected error and a control amount generated previously to control the switch circuit so that the output voltage is coincident with the target voltage according to a transfer function.
摘要翻译：一种开关调节控制器，用于驱动包括在开关调节器中的开关电路，其将输入电压转换为目标电压，并输出目标电压。开关调节控制器检测输出电压和目标电压之间的误差，并且使用检测到的误差和先前产生的控制量来控制开关电路，使得输出电压根据传递函数与目标电压一致。

6. 发明授权

US07633809B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07633809B2
公开(公告)日：2009-12-15
申请号：US11602342
申请日：2006-11-21
申请人： Shinya Kajiyama
发明人： Shinya Kajiyama
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/065 , G11C7/12 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C16/26 , H01L27/115
摘要： A semiconductor storage device in which a read sense circuit stable for the fluctuation in manufacturing process and environmental conditions can be realized and the read access time can be shortened is provided. A sense circuit for reading a memory cell characterized in that a flowing current is varied depending on stored data and a voltage applied through a word line includes: an inverter; a first capacitor provided so as to be electrically connected between an input of the inverter and a bit line to which the memory cell is connected; a first transistor which short-circuits an input and an output of the inverter; a second capacitor for supplying charge to the first capacitor; and second transistors, wherein an input potential of the inverter is increased or decreased according to the current of the memory cell and is then amplified to be latched as a logic value.
摘要翻译：一种半导体存储装置，其中可以实现对制造过程和环境条件的波动稳定的读取感测电路，并且可以缩短读取访问时间。一种用于读取存储单元的感测电路，其特征在于，流动电流根据存储的数据而变化，并且通过字线施加的电压包括：逆变器; 第一电容器，被设置为电连接在所述反相器的输入端与所述存储单元所连接的位线之间; 第一晶体管，其使逆变器的输入和输出短路; 用于向第一电容器提供电荷的第二电容器; 以及第二晶体管，其中根据存储单元的电流增加或减少反相器的输入电位，然后将其放大为锁存为逻辑值。

7. 发明授权

US06998881B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06998881B2
公开(公告)日：2006-02-14
申请号：US10948304
申请日：2004-09-24
申请人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
发明人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
IPC分类号： H03B19/00
CPC分类号： H03M9/00
摘要： In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
摘要翻译：在用于将高频的输入信号Data 1转换为低频的输出信号Data 4的电路中，只能用双极ECL电路处理的频带（例如，10GHz至2.5GHz）的信号是用双极ECL电路处理。在可以用CMOS电路处理的信号的频率达到最大频率之后，信号通过电平转换电路输入到CMOS电路，以便降低频率（例如，2.5GHz至1.25GHz）。由此，可以降低半导体集成电路器件的功耗，特别是包括Bi-CMOS电路的器件，同时保持电路的信号处理中的高种子处理特性。

8. 发明授权

US06809562B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06809562B2
公开(公告)日：2004-10-26
申请号：US10411122
申请日：2003-04-11
申请人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
发明人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
IPC分类号： H03B1900
CPC分类号： H03M9/00
摘要： In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
摘要翻译：在用于将高频输入信号Data1转换为低频输出信号Data4的电路中，仅用双极性ECL电路处理的频带（例如，10GHz至2.5GHz）的信号被处理双极ECL电路。在可以用CMOS电路处理的信号的频率达到最大频率之后，信号通过电平转换电路输入到CMOS电路，以便降低频率（例如，2.5GHz至1.25GHz）。由此，可以降低半导体集成电路器件的功耗，特别是包括Bi-CMOS电路的器件，同时保持电路的信号处理中的高种子处理特性。

9. 发明申请

US20050040869A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050040869A1
公开(公告)日：2005-02-24
申请号：US10948304
申请日：2004-09-24
申请人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
发明人： Shinichiro Wada , Satoshi Ueno , Shinya Kajiyama
IPC分类号： H01L27/06 , H01L21/8249 , H03K19/08 , H03M9/00 , H03B19/00
CPC分类号： H03M9/00
摘要： In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
摘要翻译：在用于将高频输入信号Data1转换为低频输出信号Data4的电路中，仅用双极性ECL电路处理的频带（例如，10GHz至2.5GHz）的信号被处理双极ECL电路。在可以用CMOS电路处理的信号的频率达到最大频率之后，信号通过电平转换电路输入到CMOS电路，以便降低频率（例如，2.5GHz至1.25GHz）。由此，可以降低半导体集成电路器件的功耗，特别是包括Bi-CMOS电路的器件，同时保持电路的信号处理中的高种子处理特性。

10. 发明申请

US20070121377A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070121377A1
公开(公告)日：2007-05-31
申请号：US11602342
申请日：2006-11-21
申请人： Shinya Kajiyama
发明人： Shinya Kajiyama
IPC分类号： G11C7/10
CPC分类号： G11C7/067 , G11C7/065 , G11C7/12 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C16/26 , H01L27/115
摘要： A semiconductor storage device in which a read sense circuit stable for the fluctuation in manufacturing process and environmental conditions can be realized and the read access time can be shortened is provided. A sense circuit for reading a memory cell characterized in that a flowing current is varied depending on stored data and a voltage applied through a word line includes: an inverter; a first capacitor provided so as to be electrically connected between an input of the inverter and a bit line to which the memory cell is connected; a first transistor which short-circuits an input and an output of the inverter; a second capacitor for supplying charge to the first capacitor; and second transistors, wherein an input potential of the inverter is increased or decreased according to the current of the memory cell and is then amplified to be latched as a logic value.
摘要翻译：一种半导体存储装置，其中可以实现对制造过程和环境条件的波动稳定的读取感测电路，并且可以缩短读取访问时间。一种用于读取存储单元的感测电路，其特征在于，流动电流根据存储的数据而变化，并且通过字线施加的电压包括：逆变器; 第一电容器，被设置为电连接在所述反相器的输入端与所述存储单元所连接的位线之间; 第一晶体管，其使逆变器的输入和输出短路; 用于向第一电容器提供电荷的第二电容器; 以及第二晶体管，其中根据存储单元的电流增加或减少反相器的输入电位，然后将其放大为锁存为逻辑值。

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