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1. 发明申请

US20070245176A1 BER monitoring circuit 审中-公开
标题翻译： BER监控电路
公开(公告)号：US20070245176A1
公开(公告)日：2007-10-18
申请号：US11502517
申请日：2006-08-11
申请人： Shinji Sawane , Yuji Obana , Hiroyuki Kitajima
发明人： Shinji Sawane , Yuji Obana , Hiroyuki Kitajima
IPC分类号： G06F11/00
CPC分类号： H04L1/0061 , H04L1/203
摘要： In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value is converted into a corresponding estimated error rate by a Te-BER conversion table and an alarm is generated by an SF/SD detecting -portion when the estimated error rate exceeds an alarm detecting threshold. Thereafter, the alarm is released when the estimated error rate assumes equal to or less than an alarm releasing threshold. Also, an error-free detecting portion is activated when an alarm is generated and releases the alarm when a time period for which the error cycles stay flat exceeds a cycle corresponding to the alarm releasing threshold.
摘要翻译：在BER监视电路中，通过奇偶校验部分和错误周期检测部分检测输入数据的错误周期，通过错误周期存储器和错误周期最大值检测错误周期中的最大值（平均值/中值）（平均/中值）检索部分。当估计的误码率超过警报检测阈值时，该值被转换表转换成相应的估计错误率，并通过SF / SD检测产生警报。此后，当估计误差率等于或小于报警释放阈值时，报警被释放。此外，当产生报警时，无错误检测部分被激活，并且当错误周期保持平坦的时间段超过与报警释放阈值相对应的周期时，释放报警。

2. 发明授权

US06788684B2 Cell bridge apparatus and cell bridging method as well as information transmission system having cell bridge apparatus 失效
标题翻译：单元桥装置和单元桥接方法以及具有单元桥装置的信息传输系统
公开(公告)号：US06788684B2
公开(公告)日：2004-09-07
申请号：US09201106
申请日：1998-11-30
申请人： Hiromichi Makishima , Yuji Obana , Hiroyuki Asano , Toshiaki Ookubo , Hideo Abe
发明人： Hiromichi Makishima , Yuji Obana , Hiroyuki Asano , Toshiaki Ookubo , Hideo Abe
IPC分类号： H04L1228
CPC分类号： H04L12/4625
摘要： An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.
摘要翻译： ATM信元网桥装置和信元桥接方法以及信息传输系统，具有可以在多播处理期间根据优先级顺序输出信元的单元桥接装置。 ATM单元桥接装置包括：存储输入单元的单元数据的缓冲单元;缓冲单元控制单元数据写入和读出的缓冲器控制单元;单元生成控制单元，用于管理单元的组播信息由缓冲器单元从缓冲器单元读出的数据，并产生要从单元数据的标题信息输出的单元;以及单元输出单元，用于输出由单元生成控制单元产生的单元并发出单元数据读出请求到缓冲器控制单元。

3. 发明申请

US20070253516A1 Jitter correction method and circuit 有权
标题翻译：抖动校正方法和电路
公开(公告)号：US20070253516A1
公开(公告)日：2007-11-01
申请号：US11520609
申请日：2006-09-14
申请人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
发明人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L1/205
摘要： In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.
摘要翻译：在抖动校正方法和电路中，通过将参考数据的1位时钟之后的数据的结束位和参考数据后的数据1个时钟的头位相加，结合数据组合数据。顺序地参考组合数据的每一位。当检测到参考位和与参考位直接相邻的位之间的变化时，并且当参考数量达到过采样的乘数并且未检测到包括参考位的至少三个相邻位之间的变化时，改变位置生成关于直接相邻位的显示数据作为参考数据的改变位，并且引用的数量被初始化。当未检测到变化，引用次数未达到乘数时，引用次数增加。从参考数据和改变位置显示数据中提取所有改变位，并且对应于乘数执行数据再现。

4. 发明授权

US08606118B2 Optical digital coherent receiver 有权
标题翻译：光学数字相干接收机
公开(公告)号：US08606118B2
公开(公告)日：2013-12-10
申请号：US13196997
申请日：2011-08-03
申请人： Kazuhiko Hatae , Noriyasu Nakayama , Nobukazu Koizumi , Yuji Obana
发明人： Kazuhiko Hatae , Noriyasu Nakayama , Nobukazu Koizumi , Yuji Obana
IPC分类号： H04B10/06 , H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04B10/616 , H04L25/03019 , H04L25/03248 , H04L27/223 , H04L27/3809 , H04L27/3818
摘要： An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.
摘要翻译：在自适应均衡器之后的阶段中比在光学数字相干接收机中的频率偏移估计/补偿单元早的阶段提供用于将从自适应均衡器输出的信号电平调整到目标值的ALC处理单元。 ALC处理单元产生对来自自适应均衡器的输出的振幅值对应的离散监视值的采样数进行计数的直方图，并确定要与自适应均衡器的输出相乘的电平调整系数，以便乘以通过来自自适应均衡器的输出确定的系数，使得直方图的峰值的监视值为目标值。

5. 发明授权

US5136587A Digital signal multiplexing apparatus and demultiplexing apparatus 失效
标题翻译：数字信号多路复用器和解复用器
公开(公告)号：US5136587A
公开(公告)日：1992-08-04
申请号：US576467
申请日：1990-09-07
申请人： Yuji Obana , Masanori Hiramoto , Masayuki Tanaka
发明人： Yuji Obana , Masanori Hiramoto , Masayuki Tanaka
IPC分类号： H04J3/04 , H04J3/06 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/047 , H04J3/0608 , H04J3/1611 , H04J2203/0089
摘要： A digital signal multiplexing apparatus has n (n is an arbitrary integer) multiplexing circuits (11-1n) for converting input signals from a plurality of lines into m (m is an arbitrary integer) parallel signals which are added with added bits and have a first transmission speed. A parallel-serial conversion circuit (40) converts the m parallel signals from the n multiplexing circuits into a serial multiplexed signal by a parallel-serial conversion. A bus (30) connects the n multiplexing circuits and the parallel-serial conversion circuit. The n multiplexing circuits respectively have a circuit for successively transmitting the m parallel signals to the bus using a pluse signal having a second transmission speed which is n times the first transmission speed. A digital signal demultiplexing circuit has a serial-parallel conversion circuit (75) for converting a serial input signal into m (m is an arbitrary integer) parallel signals having a predetermined transmission speed. N (n is an arbitrary integer) demultiplexing circuits (51-5n) demultiplexes added bits from the m parallel signals from the serial-parallel conversion circuit (75) and outputs the added bits on a plurality of lines with the predetermined transmission speed. A bus connects the serial-parallel conversion circuit and the n demultiplexing circuit (75). The n demultiplexing circuits respectively have a circuit for receiving the m parallel signals output on the bus from the serial-parallel conversion circuit with a clock timing of a speed identical to the predetermined transmission speed.
摘要翻译： PCT No.PCT / JP90 / 00011 Sec。 371 1990年9月7日第 102（e）1990年9月7日PCT PCT 1990年1月8日PCT公布。出版物WO90 / 07829 日期：1990年7月12日。数字信号复用装置具有用于将来自多条线路的输入信号转换为m（m为任意整数）并行信号的n（n为任意整数）复用电路（11-1n）添加了比特，并具有第一个传输速度。并行串行转换电路（40）通过并行串行转换将来自n个多路复用电路的m个并行信号转换为串行复用信号。总线（30）连接n个多路复用电路和并行串行转换电路。 n个多路复用电路分别具有使用具有n倍于第一传输速度的第二传输速度的pluse信号将m个并行信号连续发送到总线的电路。数字信号解复用电路具有用于将串行输入信号转换成具有预定传输速度的m（m是任意整数）并行信号的串并转换电路（75）。 N（n是任意整数）解复用电路（51-5n）从来自串行 - 并行转换电路（75）的m个并行信号中分离出相加的比特，并以预定的传输速度输出多条线上的相加比特。总线连接串并转换电路和n解复用电路（75）。 n个解复用电路分别具有用于以与预定传输速度相同的速度的时钟定时从串行/并行转换电路接收在总线上输出的m个并行信号的电路。

6. 发明授权

US08000429B2 Jitter correction method and circuit 有权
标题翻译：抖动校正方法和电路
公开(公告)号：US08000429B2
公开(公告)日：2011-08-16
申请号：US11520609
申请日：2006-09-14
申请人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
发明人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L1/205
摘要： In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.
摘要翻译：在抖动校正方法和电路中，通过将参考数据的1位时钟之后的数据的结束位和参考数据后的数据1个时钟的头位相加，结合数据组合数据。顺序地参考组合数据的每一位。当检测到参考位和与参考位直接相邻的位之间的变化时，并且当参考数量达到过采样的乘数并且未检测到包括参考位的至少三个相邻位之间的变化时，改变位置生成关于直接相邻位的显示数据作为参考数据的改变位，并且引用的数量被初始化。当未检测到变化，引用次数未达到乘数时，引用次数增加。从参考数据和改变位置显示数据中提取所有改变位，并且对应于乘数执行数据再现。

7. 发明授权

US07397882B2 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion 有权
标题翻译：数字锁相电路能够处理以突发方式提供的输入时钟信号
公开(公告)号：US07397882B2
公开(公告)日：2008-07-08
申请号：US10671593
申请日：2003-09-29
申请人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
发明人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
IPC分类号： H03D3/24
CPC分类号： H03L7/0993 , H03L7/107 , H04J3/076
摘要： A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.
摘要翻译：数字锁相电路提供输出时钟信号，其输出时钟信号的相位与期望的相位吸收特性水平下的输入时钟信号的相位同步，即使以突发方式提供输入时钟信号。相位比较部分将输出时钟信号的相位与输入时钟信号的相位进行比较。相位比较结果检测部分输出用于根据相位比较信号控制除法运算的INC / DEC请求信号。执行率计算部分根据INC / DEC请求信号计算输入时钟信号和输出时钟信号之间的相位差，并输出与相位差对应的执行速率。时钟产生部分根据INC / DEC请求信号控制主时钟信号的除法运算，并根据执行速率改变输出时钟信号的相位吸收速度。

8. 发明授权

US5001711A Complex multiplexer/demultiplexer apparatus 失效
标题翻译：复合多路复用器/解复用器装置
公开(公告)号：US5001711A
公开(公告)日：1991-03-19
申请号：US389264
申请日：1989-08-03
申请人： Yuji Obana , Masanori Hiramoto
发明人： Yuji Obana , Masanori Hiramoto
IPC分类号： H04J3/00 , H04J3/06 , H04J3/07 , H04J3/16
CPC分类号： H04J3/073 , H04J3/1641 , H04J3/0685
摘要： A complex multiplexer/demultiplexer apparatus which converts input low order group data signals to middle order group data signals and multiplexes them to high order group data signals and converts high order group data signals to middle order group data signals and demultiplexes them to low order group data signals, wherein a plurality of low order group channels are processed by multiplexing and demultiplexing at a second clock bit synchronized with a first clock on the high order group side, the second clock including empty bits, and the bit rate being set lower than the first clock, and signal speeds between each of first multiplexers and a second multiplexer and between a first demultiplexer and each of second demultiplexers are converted by insertion and deletion of the empty bits which may have inserted therein additional information.

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